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    d22e9a6d
    drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP · d22e9a6d
    Liu Ying authored
    
    According to Synopsys support channel, each region of HSA, HBP and HFP must
    have minimum number of 10 bytes where constant 4 bytes are for HSS or HSE
    and 6 bytes are for blanking packet(header + CRC).  Hence, the below table
    comes in.
    
    +------------+----------+-------+
    | data lanes | min lbcc | bytes |
    +------------+----------+-------+
    |     1      |    10    |  1*10 |
    +------------+----------+-------+
    |     2      |    5     |  2*5  |
    +------------+----------+-------+
    |     3      |    4     |  3*4  |
    +------------+----------+-------+
    |     4      |    3     |  4*3  |
    +------------+----------+-------+
    
    Implement the minimum lbcc numbers to make sure that the values programmed
    into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum
    number requirement.  For DSI_VID_HLINE_TIME register, it seems that the
    value programmed should be based on mode->htotal as-is, instead of sum up
    HSA, HBP, HFP and HDISPLAY.
    
    This helps the case where Raydium RM67191 DSI panel is connected, since
    it's video timing for hsync length is only 2 pixels and without this patch
    the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes.
    
    Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
    Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
    Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
    Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-7-victor.liu@nxp.com
    drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP
    Liu Ying authored
    
    According to Synopsys support channel, each region of HSA, HBP and HFP must
    have minimum number of 10 bytes where constant 4 bytes are for HSS or HSE
    and 6 bytes are for blanking packet(header + CRC).  Hence, the below table
    comes in.
    
    +------------+----------+-------+
    | data lanes | min lbcc | bytes |
    +------------+----------+-------+
    |     1      |    10    |  1*10 |
    +------------+----------+-------+
    |     2      |    5     |  2*5  |
    +------------+----------+-------+
    |     3      |    4     |  3*4  |
    +------------+----------+-------+
    |     4      |    3     |  4*3  |
    +------------+----------+-------+
    
    Implement the minimum lbcc numbers to make sure that the values programmed
    into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum
    number requirement.  For DSI_VID_HLINE_TIME register, it seems that the
    value programmed should be based on mode->htotal as-is, instead of sum up
    HSA, HBP, HFP and HDISPLAY.
    
    This helps the case where Raydium RM67191 DSI panel is connected, since
    it's video timing for hsync length is only 2 pixels and without this patch
    the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes.
    
    Signed-off-by: default avatarLiu Ying <victor.liu@nxp.com>
    Reviewed-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
    Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
    Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-7-victor.liu@nxp.com