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  1. Oct 18, 2023
  2. Oct 13, 2023
  3. Oct 04, 2023
    • Adrián Larumbe's avatar
      drm/panfrost: Add fdinfo support GPU load metrics · f11b0417
      Adrián Larumbe authored
      
      The drm-stats fdinfo tags made available to user space are drm-engine,
      drm-cycles, drm-max-freq and drm-curfreq, one per job slot.
      
      This deviates from standard practice in other DRM drivers, where a single
      set of key:value pairs is provided for the whole render engine. However,
      Panfrost has separate queues for fragment and vertex/tiler jobs, so a
      decision was made to calculate bus cycles and workload times separately.
      
      Maximum operating frequency is calculated at devfreq initialisation time.
      Current frequency is made available to user space because nvtop uses it
      when performing engine usage calculations.
      
      It is important to bear in mind that both GPU cycle and kernel time numbers
      provided are at best rough estimations, and always reported in excess from
      the actual figure because of two reasons:
       - Excess time because of the delay between the end of a job processing,
         the subsequent job IRQ and the actual time of the sample.
       - Time spent in the engine queue waiting for the GPU to pick up the next
         job.
      
      To avoid race conditions during enablement/disabling, a reference counting
      mechanism was introduced, and a job flag that tells us whether a given job
      increased the refcount. This is necessary, because user space can toggle
      cycle counting through a debugfs file, and a given job might have been in
      flight by the time cycle counting was disabled.
      
      The main goal of the debugfs cycle counter knob is letting tools like nvtop
      or IGT's gputop switch it at any time, to avoid power waste in case no
      engine usage measuring is necessary.
      
      Also add a documentation file explaining the possible values for fdinfo's
      engine keystrings and Panfrost-specific drm-curfreq-<keystr> pairs.
      
      Signed-off-by: default avatarAdrián Larumbe <adrian.larumbe@collabora.com>
      Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
      Reviewed-by: default avatarSteven Price <steven.price@arm.com>
      Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
      Signed-off-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20230929181616.2769345-3-adrian.larumbe@collabora.com
      f11b0417
  4. Sep 28, 2023
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  13. Sep 01, 2023
    • Lad Prabhakar's avatar
      cache: Add L2 cache management for Andes AX45MP RISC-V core · d34599bc
      Lad Prabhakar authored
      I/O Coherence Port (IOCP) provides an AXI interface for connecting
      external non-caching masters, such as DMA controllers. The accesses
      from IOCP are coherent with D-Caches and L2 Cache.
      
      IOCP is a specification option and is disabled on the Renesas RZ/Five
      SoC due to this reason IP blocks using DMA will fail.
      
      The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
      block that allows dynamic adjustment of memory attributes in the runtime.
      It contains a configurable amount of PMA entries implemented as CSR
      registers to control the attributes of memory locations in interest.
      Below are the memory attributes supported:
      * Device, Non-bufferable
      * Device, bufferable
      * Memory, Non-cacheable, Non-bufferable
      * Memory, Non-cacheable, Bufferable
      * Memory, Write-back, No-allocate
      * Memory, Write-back, Read-allocate
      * Memory, Write-back, Write-allocate
      * Memory, Write-back, Read and Write-allocate
      
      More info about PMA (section 10.3):
      Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
      
      
      
      As a workaround for SoCs with IOCP disabled CMO needs to be handled by
      software. Firstly OpenSBI configures the memory region as
      "Memory, Non-cacheable, Bufferable" and passes this region as a global
      shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
      allocations happen from this region and synchronization callbacks are
      implemented to synchronize when doing DMA transactions.
      
      Example PMA region passes as a DT node from OpenSBI:
          reserved-memory {
              #address-cells = <2>;
              #size-cells = <2>;
              ranges;
      
              pma_resv0@58000000 {
                  compatible = "shared-dma-pool";
                  reg = <0x0 0x58000000 0x0 0x08000000>;
                  no-map;
                  linux,dma-default;
              };
          };
      
      Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
      Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
      Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
      Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.com
      
      
      Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
      d34599bc
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