xtensa: add load/store exception handler
Memory attached to instruction bus of the xtensa CPU is only accessible
for a limited subset of opcodes. Other opcodes generate an exception
with the load/store error cause code. This property complicates use of
such systems. Provide a handler that recognizes and transparently fixes
such exceptions. The following opcodes are recognized when used outside
of FLIX bundles: l32i, l32i.n, l16ui, l16si, l8ui.
Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com>
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- arch/xtensa/Kconfig 12 additions, 0 deletionsarch/xtensa/Kconfig
- arch/xtensa/include/asm/traps.h 5 additions, 0 deletionsarch/xtensa/include/asm/traps.h
- arch/xtensa/kernel/align.S 97 additions, 12 deletionsarch/xtensa/kernel/align.S
- arch/xtensa/kernel/setup.c 2 additions, 1 deletionarch/xtensa/kernel/setup.c
- arch/xtensa/kernel/traps.c 20 additions, 1 deletionarch/xtensa/kernel/traps.c
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