drm/radeon/kms: Schedule host path read cache flush through the ring V2
R300 family will hard lockup if host path read cache flush is done through MMIO to HOST_PATH_CNTL. But scheduling same flush through ring seems harmless. This patch remove the hdp_flush callback and add a flush after each fence emission which means a flush after each IB schedule. Thus we should have same behavior without the hard lockup. Tested on R100,R200,R300,R400,R500,R600,R700 family. V2: Adjust fence counts in r600_blit_prepare_copy() Signed-off-by:Jerome Glisse <jglisse@redhat.com> Reviewed-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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- drivers/gpu/drm/radeon/r100.c 6 additions, 8 deletionsdrivers/gpu/drm/radeon/r100.c
- drivers/gpu/drm/radeon/r300.c 15 additions, 1 deletiondrivers/gpu/drm/radeon/r300.c
- drivers/gpu/drm/radeon/r420.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/r420.c
- drivers/gpu/drm/radeon/r520.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/r520.c
- drivers/gpu/drm/radeon/r600.c 2 additions, 5 deletionsdrivers/gpu/drm/radeon/r600.c
- drivers/gpu/drm/radeon/r600_blit_kms.c 2 additions, 2 deletionsdrivers/gpu/drm/radeon/r600_blit_kms.c
- drivers/gpu/drm/radeon/radeon.h 2 additions, 2 deletionsdrivers/gpu/drm/radeon/radeon.h
- drivers/gpu/drm/radeon/radeon_asic.h 0 additions, 12 deletionsdrivers/gpu/drm/radeon/radeon_asic.h
- drivers/gpu/drm/radeon/radeon_gem.c 0 additions, 2 deletionsdrivers/gpu/drm/radeon/radeon_gem.c
- drivers/gpu/drm/radeon/rs400.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/rs400.c
- drivers/gpu/drm/radeon/rs600.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/rs600.c
- drivers/gpu/drm/radeon/rs690.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/rs690.c
- drivers/gpu/drm/radeon/rv515.c 1 addition, 0 deletionsdrivers/gpu/drm/radeon/rv515.c
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