drm/nouveau/fifo/nvc0-: use interrupt 31 as an event trigger
Generated if you try and use fifo method 0x20 on any subchannel, appears
that it can be safely masked off without stalling the whole GPU.
Signed-off-by: 
Ben Skeggs <bskeggs@redhat.com>
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- drivers/gpu/drm/nouveau/core/engine/fifo/base.c 6 additions, 0 deletionsdrivers/gpu/drm/nouveau/core/engine/fifo/base.c
- drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c 22 additions, 2 deletionsdrivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
- drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c 26 additions, 1 deletiondrivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
- drivers/gpu/drm/nouveau/core/include/engine/fifo.h 2 additions, 0 deletionsdrivers/gpu/drm/nouveau/core/include/engine/fifo.h
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