diff --git a/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h b/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
deleted file mode 100644
index 8cce7f15b6eb9774f5ba547ed87c90d2f9a0f0bc..0000000000000000000000000000000000000000
--- a/drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * Intentionally empty file.
- */
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
deleted file mode 100644
index 69c4253fbfbb1be32d22b43aa631287ff7d3deb8..0000000000000000000000000000000000000000
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/**********************************************************
- * Copyright 2007-2015 VMware, Inc.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *
- **********************************************************/
-
-/*
- * svga3d_caps.h --
- *
- * Definitions for SVGA3D hardware capabilities. Capabilities
- * are used to query for optional rendering features during
- * driver initialization. The capability data is stored as very
- * basic key/value dictionary within the "FIFO register" memory
- * area at the beginning of BAR2.
- *
- * Note that these definitions are only for 3D capabilities.
- * The SVGA device also has "device capabilities" and "FIFO
- * capabilities", which are non-3D-specific and are stored as
- * bitfields rather than key/value pairs.
- */
-
-#ifndef _SVGA3D_CAPS_H_
-#define _SVGA3D_CAPS_H_
-
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-
-#include "includeCheck.h"
-
-#include "svga_reg.h"
-
-#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
- SVGA_FIFO_3D_CAPS + 1)
-
-
-/*
- * SVGA3dCapsRecordType
- *
- * Record types that can be found in the caps block.
- * Related record types are grouped together numerically so that
- * SVGA3dCaps_FindRecord() can be applied on a range of record
- * types.
- */
-
-typedef enum {
- SVGA3DCAPS_RECORD_UNKNOWN = 0,
- SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
- SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
- SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
-} SVGA3dCapsRecordType;
-
-
-/*
- * SVGA3dCapsRecordHeader
- *
- * Header field leading each caps block record. Contains the offset (in
- * register words, NOT bytes) to the next caps block record (or the end
- * of caps block records which will be a zero word) and the record type
- * as defined above.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCapsRecordHeader {
- uint32 length;
- SVGA3dCapsRecordType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCapsRecordHeader;
-
-
-/*
- * SVGA3dCapsRecord
- *
- * Caps block record; "data" is a placeholder for the actual data structure
- * contained within the record;
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCapsRecord {
- SVGA3dCapsRecordHeader header;
- uint32 data[1];
-}
-#include "vmware_pack_end.h"
-SVGA3dCapsRecord;
-
-
-typedef uint32 SVGA3dCapPair[2];
-
-#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
index 799bc0963f7a134d565568737367769b27c72bb9..945c84b27e814f990e04a8b3facd18a72fc5ea3d 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 1998-2020 VMware, Inc.
+ * Copyright 2012-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,2249 +27,1487 @@
/*
* svga3d_cmd.h --
*
- * SVGA 3d hardware cmd definitions
+ * SVGA 3d hardware cmd definitions
*/
+
+
#ifndef _SVGA3D_CMD_H_
#define _SVGA3D_CMD_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-
-#include "includeCheck.h"
#include "svga3d_types.h"
-
-/*
- * Identifiers for commands in the command FIFO.
- *
- * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
- * the SVGA3D protocol and remain reserved; they should not be used in the
- * future.
- *
- * IDs between 1040 and 2999 (inclusive) are available for use by the
- * current SVGA3D protocol.
- *
- * FIFO clients other than SVGA3D should stay below 1000, or at 3000
- * and up.
- */
-
-typedef enum {
- SVGA_3D_CMD_LEGACY_BASE = 1000,
- SVGA_3D_CMD_BASE = 1040,
-
- SVGA_3D_CMD_SURFACE_DEFINE = 1040,
- SVGA_3D_CMD_SURFACE_DESTROY = 1041,
- SVGA_3D_CMD_SURFACE_COPY = 1042,
- SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
- SVGA_3D_CMD_SURFACE_DMA = 1044,
- SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
- SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
- SVGA_3D_CMD_SETTRANSFORM = 1047,
- SVGA_3D_CMD_SETZRANGE = 1048,
- SVGA_3D_CMD_SETRENDERSTATE = 1049,
- SVGA_3D_CMD_SETRENDERTARGET = 1050,
- SVGA_3D_CMD_SETTEXTURESTATE = 1051,
- SVGA_3D_CMD_SETMATERIAL = 1052,
- SVGA_3D_CMD_SETLIGHTDATA = 1053,
- SVGA_3D_CMD_SETLIGHTENABLED = 1054,
- SVGA_3D_CMD_SETVIEWPORT = 1055,
- SVGA_3D_CMD_SETCLIPPLANE = 1056,
- SVGA_3D_CMD_CLEAR = 1057,
- SVGA_3D_CMD_PRESENT = 1058,
- SVGA_3D_CMD_SHADER_DEFINE = 1059,
- SVGA_3D_CMD_SHADER_DESTROY = 1060,
- SVGA_3D_CMD_SET_SHADER = 1061,
- SVGA_3D_CMD_SET_SHADER_CONST = 1062,
- SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
- SVGA_3D_CMD_SETSCISSORRECT = 1064,
- SVGA_3D_CMD_BEGIN_QUERY = 1065,
- SVGA_3D_CMD_END_QUERY = 1066,
- SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
- SVGA_3D_CMD_PRESENT_READBACK = 1068,
- SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
- SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
- SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
- SVGA_3D_CMD_DEAD4 = 1072,
- SVGA_3D_CMD_DEAD5 = 1073,
- SVGA_3D_CMD_DEAD6 = 1074,
- SVGA_3D_CMD_DEAD7 = 1075,
- SVGA_3D_CMD_DEAD8 = 1076,
- SVGA_3D_CMD_DEAD9 = 1077,
- SVGA_3D_CMD_DEAD10 = 1078,
- SVGA_3D_CMD_DEAD11 = 1079,
- SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
- SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
- SVGA_3D_CMD_SCREEN_DMA = 1082,
- SVGA_3D_CMD_DEAD1 = 1083,
- SVGA_3D_CMD_DEAD2 = 1084,
-
- SVGA_3D_CMD_DEAD12 = 1085,
- SVGA_3D_CMD_DEAD13 = 1086,
- SVGA_3D_CMD_DEAD14 = 1087,
- SVGA_3D_CMD_DEAD15 = 1088,
- SVGA_3D_CMD_DEAD16 = 1089,
- SVGA_3D_CMD_DEAD17 = 1090,
-
- SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
- SVGA_3D_CMD_READBACK_OTABLE = 1092,
-
- SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
- SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
- SVGA_3D_CMD_DEAD3 = 1095,
- SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
-
- SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
- SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
- SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
- SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
- SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
- SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
- SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
- SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
- SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
- SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
-
- SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
- SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
- SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
- SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
- SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
-
- SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
- SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
- SVGA_3D_CMD_BIND_GB_SHADER = 1114,
-
- SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
-
- SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
- SVGA_3D_CMD_END_GB_QUERY = 1117,
- SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
-
- SVGA_3D_CMD_NOP = 1119,
-
- SVGA_3D_CMD_ENABLE_GART = 1120,
- SVGA_3D_CMD_DISABLE_GART = 1121,
- SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
- SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
-
- SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
- SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
- SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
- SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
-
- SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
- SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
-
- SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
-
- SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
- SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
- SVGA_3D_CMD_GB_MOB_FENCE = 1133,
- SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
- SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
- SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
- SVGA_3D_CMD_NOP_ERROR = 1137,
-
- SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
- SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
- SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
- SVGA_3D_CMD_DRAW = 1141,
- SVGA_3D_CMD_DRAW_INDEXED = 1142,
-
- /*
- * DX10 Commands
- */
- SVGA_3D_CMD_DX_MIN = 1143,
- SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
- SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
- SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
- SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
- SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
- SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
- SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
- SVGA_3D_CMD_DX_SET_SHADER = 1150,
- SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
- SVGA_3D_CMD_DX_DRAW = 1152,
- SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
- SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
- SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
- SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
- SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
- SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
- SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
- SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
- SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
- SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
- SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
- SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
- SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
- SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
- SVGA_3D_CMD_DX_BIND_QUERY = 1167,
- SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
- SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
- SVGA_3D_CMD_DX_END_QUERY = 1170,
- SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
- SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
- SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
- SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
- SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
- SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
- SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
- SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
- SVGA_3D_CMD_DX_PRED_COPY = 1179,
- SVGA_3D_CMD_DX_PRESENTBLT = 1180,
- SVGA_3D_CMD_DX_GENMIPS = 1181,
- SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
- SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
- SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
- SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
- SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
- SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
- SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
- SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
- SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
- SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
- SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
- SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
- SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
- SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
- SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
- SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
- SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
- SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
- SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
- SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
- SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
- SVGA_3D_CMD_DX_BIND_SHADER = 1203,
- SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
- SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
- SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
- SVGA_3D_CMD_DX_SET_COTABLE = 1207,
- SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
- SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
- SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
- SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
- SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
- SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
- SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
- SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
- SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
- SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
- SVGA_3D_CMD_DX_HINT = 1218,
- SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
- SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
- SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
- SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
- SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
- SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
- SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,
-
- SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
- SVGA_3D_CMD_DX_MAX = 1227,
-
- SVGA_3D_CMD_SCREEN_COPY = 1227,
-
- SVGA_3D_CMD_RESERVED1 = 1228,
- SVGA_3D_CMD_RESERVED2 = 1229,
- SVGA_3D_CMD_RESERVED3 = 1230,
- SVGA_3D_CMD_RESERVED4 = 1231,
- SVGA_3D_CMD_RESERVED5 = 1232,
- SVGA_3D_CMD_RESERVED6 = 1233,
- SVGA_3D_CMD_RESERVED7 = 1234,
- SVGA_3D_CMD_RESERVED8 = 1235,
-
- SVGA_3D_CMD_GROW_OTABLE = 1236,
- SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
- SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
-
- SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
-
- SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
- SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
- SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
- SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
- SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
-
- SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
- SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
- SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
- SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
- SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
- SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,
-
- SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
- SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
- SVGA_3D_CMD_DX_DISPATCH = 1253,
- SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,
-
- SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
- SVGA_3D_CMD_HINT_ZERO_SURFACE = 1256,
- SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
- SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,
-
- SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
- SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
- SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
- SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
- SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
- SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,
-
- SVGA_3D_CMD_RESERVED2_1 = 1265,
-
- SVGA_3D_CMD_RESERVED2_2 = 1266,
- SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
- SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
- SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
- SVGA_3D_CMD_RESERVED2_3 = 1270,
- SVGA_3D_CMD_RESERVED2_4 = 1271,
- SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
- SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
- SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
- SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
- SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
- SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,
-
- SVGA_3D_CMD_MAX = 1278,
- SVGA_3D_CMD_FUTURE_MAX = 3000
+#include "svga3d_limits.h"
+#include "svga_reg.h"
+
+typedef enum SVGAFifo3dCmdId {
+ SVGA_3D_CMD_LEGACY_BASE = 1000,
+ SVGA_3D_CMD_BASE = 1040,
+
+ SVGA_3D_CMD_SURFACE_DEFINE = 1040,
+ SVGA_3D_CMD_SURFACE_DESTROY = 1041,
+ SVGA_3D_CMD_SURFACE_COPY = 1042,
+ SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
+ SVGA_3D_CMD_SURFACE_DMA = 1044,
+ SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
+ SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
+ SVGA_3D_CMD_SETTRANSFORM = 1047,
+ SVGA_3D_CMD_SETZRANGE = 1048,
+ SVGA_3D_CMD_SETRENDERSTATE = 1049,
+ SVGA_3D_CMD_SETRENDERTARGET = 1050,
+ SVGA_3D_CMD_SETTEXTURESTATE = 1051,
+ SVGA_3D_CMD_SETMATERIAL = 1052,
+ SVGA_3D_CMD_SETLIGHTDATA = 1053,
+ SVGA_3D_CMD_SETLIGHTENABLED = 1054,
+ SVGA_3D_CMD_SETVIEWPORT = 1055,
+ SVGA_3D_CMD_SETCLIPPLANE = 1056,
+ SVGA_3D_CMD_CLEAR = 1057,
+ SVGA_3D_CMD_PRESENT = 1058,
+ SVGA_3D_CMD_SHADER_DEFINE = 1059,
+ SVGA_3D_CMD_SHADER_DESTROY = 1060,
+ SVGA_3D_CMD_SET_SHADER = 1061,
+ SVGA_3D_CMD_SET_SHADER_CONST = 1062,
+ SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
+ SVGA_3D_CMD_SETSCISSORRECT = 1064,
+ SVGA_3D_CMD_BEGIN_QUERY = 1065,
+ SVGA_3D_CMD_END_QUERY = 1066,
+ SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
+ SVGA_3D_CMD_PRESENT_READBACK = 1068,
+ SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
+ SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
+ SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
+ SVGA_3D_CMD_DEAD4 = 1072,
+ SVGA_3D_CMD_DEAD5 = 1073,
+ SVGA_3D_CMD_DEAD6 = 1074,
+ SVGA_3D_CMD_DEAD7 = 1075,
+ SVGA_3D_CMD_DEAD8 = 1076,
+ SVGA_3D_CMD_DEAD9 = 1077,
+ SVGA_3D_CMD_DEAD10 = 1078,
+ SVGA_3D_CMD_DEAD11 = 1079,
+ SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
+ SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
+ SVGA_3D_CMD_SCREEN_DMA = 1082,
+ SVGA_3D_CMD_DEAD1 = 1083,
+ SVGA_3D_CMD_DEAD2 = 1084,
+
+ SVGA_3D_CMD_DEAD12 = 1085,
+ SVGA_3D_CMD_DEAD13 = 1086,
+ SVGA_3D_CMD_DEAD14 = 1087,
+ SVGA_3D_CMD_DEAD15 = 1088,
+ SVGA_3D_CMD_DEAD16 = 1089,
+ SVGA_3D_CMD_DEAD17 = 1090,
+
+ SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
+ SVGA_3D_CMD_READBACK_OTABLE = 1092,
+
+ SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
+ SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
+ SVGA_3D_CMD_DEAD3 = 1095,
+ SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
+
+ SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
+ SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
+ SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
+ SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
+ SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
+ SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
+ SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
+ SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
+ SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
+ SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
+
+ SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
+ SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
+ SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
+ SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
+ SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
+
+ SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
+ SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
+ SVGA_3D_CMD_BIND_GB_SHADER = 1114,
+
+ SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
+
+ SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
+ SVGA_3D_CMD_END_GB_QUERY = 1117,
+ SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
+
+ SVGA_3D_CMD_NOP = 1119,
+
+ SVGA_3D_CMD_ENABLE_GART = 1120,
+ SVGA_3D_CMD_DISABLE_GART = 1121,
+ SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
+ SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
+
+ SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
+ SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
+ SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
+ SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
+
+ SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
+ SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
+
+ SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
+
+ SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
+ SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
+ SVGA_3D_CMD_GB_MOB_FENCE = 1133,
+ SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
+ SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
+ SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
+ SVGA_3D_CMD_NOP_ERROR = 1137,
+
+ SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
+ SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
+ SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
+ SVGA_3D_CMD_DRAW = 1141,
+ SVGA_3D_CMD_DRAW_INDEXED = 1142,
+
+ SVGA_3D_CMD_DX_MIN = 1143,
+ SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
+ SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
+ SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
+ SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
+ SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
+ SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
+ SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
+ SVGA_3D_CMD_DX_SET_SHADER = 1150,
+ SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
+ SVGA_3D_CMD_DX_DRAW = 1152,
+ SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
+ SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
+ SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
+ SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
+ SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
+ SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
+ SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
+ SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
+ SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
+ SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
+ SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
+ SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
+ SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
+ SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
+ SVGA_3D_CMD_DX_BIND_QUERY = 1167,
+ SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
+ SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
+ SVGA_3D_CMD_DX_END_QUERY = 1170,
+ SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
+ SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
+ SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
+ SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
+ SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
+ SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
+ SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
+ SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
+ SVGA_3D_CMD_DX_PRED_COPY = 1179,
+ SVGA_3D_CMD_DX_PRESENTBLT = 1180,
+ SVGA_3D_CMD_DX_GENMIPS = 1181,
+ SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
+ SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
+ SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
+ SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
+ SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
+ SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
+ SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
+ SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
+ SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
+ SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
+ SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
+ SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
+ SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
+ SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
+ SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
+ SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
+ SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
+ SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
+ SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
+ SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
+ SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
+ SVGA_3D_CMD_DX_BIND_SHADER = 1203,
+ SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
+ SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
+ SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
+ SVGA_3D_CMD_DX_SET_COTABLE = 1207,
+ SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
+ SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
+ SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
+ SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
+ SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
+ SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
+ SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
+ SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
+ SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
+ SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
+ SVGA_3D_CMD_DX_HINT = 1218,
+ SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
+ SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
+ SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
+ SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
+ SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
+ SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
+ SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,
+
+ SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
+ SVGA_3D_CMD_DX_MAX = 1227,
+
+ SVGA_3D_CMD_SCREEN_COPY = 1227,
+
+ SVGA_3D_CMD_RESERVED1 = 1228,
+ SVGA_3D_CMD_RESERVED2 = 1229,
+ SVGA_3D_CMD_RESERVED3 = 1230,
+ SVGA_3D_CMD_RESERVED4 = 1231,
+ SVGA_3D_CMD_RESERVED5 = 1232,
+ SVGA_3D_CMD_RESERVED6 = 1233,
+ SVGA_3D_CMD_RESERVED7 = 1234,
+ SVGA_3D_CMD_RESERVED8 = 1235,
+
+ SVGA_3D_CMD_GROW_OTABLE = 1236,
+ SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
+ SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
+
+ SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
+
+ SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
+ SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
+ SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
+ SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
+ SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
+
+ SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
+ SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
+ SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
+ SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
+ SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
+ SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,
+
+ SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
+ SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
+ SVGA_3D_CMD_DX_DISPATCH = 1253,
+ SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,
+
+ SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
+ SVGA_3D_CMD_UPDATE_ZERO_SURFACE = 1256,
+ SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
+ SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,
+
+ SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
+ SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
+ SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
+ SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
+ SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
+ SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,
+
+ SVGA_3D_CMD_DX_COPY_COTABLE_INTO_MOB = 1265,
+
+ SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_V2 = 1266,
+
+ SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
+ SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
+ SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
+
+ SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
+ SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
+ SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
+ SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
+ SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
+ SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,
+
+ SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_MOVE = 1278,
+
+ SVGA_3D_CMD_DX_PRED_STAGING_COPY = 1281,
+ SVGA_3D_CMD_DX_STAGING_COPY = 1282,
+ SVGA_3D_CMD_DX_PRED_STAGING_COPY_REGION = 1283,
+ SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_V2 = 1284,
+ SVGA_3D_CMD_DX_SET_INDEX_BUFFER_V2 = 1285,
+ SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_OFFSET_AND_SIZE = 1286,
+ SVGA_3D_CMD_DX_SET_INDEX_BUFFER_OFFSET_AND_SIZE = 1287,
+ SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE_V2 = 1288,
+ SVGA_3D_CMD_DX_PRED_STAGING_CONVERT_REGION = 1289,
+ SVGA_3D_CMD_DX_PRED_STAGING_CONVERT = 1290,
+ SVGA_3D_CMD_DX_STAGING_BUFFER_COPY = 1291,
+
+ SVGA_3D_CMD_MAX = 1303,
+ SVGA_3D_CMD_FUTURE_MAX = 3000
} SVGAFifo3dCmdId;
#define SVGA_NUM_3D_CMD (SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)
-/*
- * FIFO command format definitions:
- */
-
-/*
- * The data size header following cmdNum for every 3d command
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 id;
- uint32 size;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdHeader;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 numMipLevels;
-}
-#include "vmware_pack_end.h"
-SVGA3dSurfaceFace;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- SVGA3dSurface1Flags surfaceFlags;
- SVGA3dSurfaceFormat format;
-
- /*
- * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
- * structures must have the same value of numMipLevels field.
- * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
- * numMipLevels set to 0.
- */
- SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
-
- /*
- * Followed by an SVGA3dSize structure for each mip level in each face.
- *
- * A note on surface sizes: Sizes are always specified in pixels,
- * even if the true surface size is not a multiple of the minimum
- * block size of the surface's format. For example, a 3x3x1 DXT1
- * compressed texture would actually be stored as a 4x4x1 image in
- * memory.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- SVGA3dSurface1Flags surfaceFlags;
- SVGA3dSurfaceFormat format;
-
- /*
- * If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
- * structures must have the same value of numMipLevels field.
- * Otherwise, all but the first SVGA3dSurfaceFace structures must have the
- * numMipLevels set to 0.
- */
- SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
- uint32 multisampleCount;
- SVGA3dTextureFilter autogenFilter;
-
- /*
- * Followed by an SVGA3dSize structure for each mip level in each face.
- *
- * A note on surface sizes: Sizes are always specified in pixels,
- * even if the true surface size is not a multiple of the minimum
- * block size of the surface's format. For example, a 3x3x1 DXT1
- * compressed texture would actually be stored as a 4x4x1 image in
- * memory.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dClearFlag clearFlag;
- uint32 color;
- float depth;
- uint32 stencil;
- /* Followed by variable number of SVGA3dRect structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dLightType type;
- SVGA3dBool inWorldSpace;
- float diffuse[4];
- float specular[4];
- float ambient[4];
- float position[4];
- float direction[4];
- float range;
- float falloff;
- float attenuation0;
- float attenuation1;
- float attenuation2;
- float theta;
- float phi;
-}
-#include "vmware_pack_end.h"
-SVGA3dLightData;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- /* Followed by variable number of SVGA3dCopyRect structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dRenderStateName state;
- union {
- uint32 uintValue;
- float floatValue;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dRenderState;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- /* Followed by variable number of SVGA3dRenderState structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dRenderTargetType type;
- SVGA3dSurfaceImageId target;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dest;
- /* Followed by variable number of SVGA3dCopyBox structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
+#pragma pack(push, 1)
+typedef struct {
+ uint32 id;
+ uint32 size;
+} SVGA3dCmdHeader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 numMipLevels;
+} SVGA3dSurfaceFace;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+ SVGA3dSurface1Flags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+
+ SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
+
+} SVGA3dCmdDefineSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+ SVGA3dSurface1Flags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+
+ SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
+ uint32 multisampleCount;
+ SVGA3dTextureFilter autogenFilter;
+
+} SVGA3dCmdDefineSurface_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+} SVGA3dCmdDestroySurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+} SVGA3dCmdDefineContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+} SVGA3dCmdDestroyContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dClearFlag clearFlag;
+ uint32 color;
+ float depth;
+ uint32 stencil;
+
+} SVGA3dCmdClear;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dLightType type;
+ SVGA3dBool inWorldSpace;
+ float diffuse[4];
+ float specular[4];
+ float ambient[4];
+ float position[4];
+ float direction[4];
+ float range;
+ float falloff;
+ float attenuation0;
+ float attenuation1;
+ float attenuation2;
+ float theta;
+ float phi;
+} SVGA3dLightData;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+
+} SVGA3dCmdPresent;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dRenderStateName state;
+ union {
+ uint32 uintValue;
+ float floatValue;
+ };
+} SVGA3dRenderState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+} SVGA3dCmdSetRenderState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dRenderTargetType type;
+ SVGA3dSurfaceImageId target;
+} SVGA3dCmdSetRenderTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dest;
+
+} SVGA3dCmdSurfaceCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId surface;
+ SVGA3dCopyBox box;
+} SVGA3dCmdIntraSurfaceCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 srcSid;
+ uint32 destSid;
+} SVGA3dCmdWholeSurfaceCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dest;
+ SVGA3dBox boxSrc;
+ SVGA3dBox boxDest;
+} SVGA3dCmdSurfaceStretchBltNonMSToMS;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dest;
+ SVGA3dBox boxSrc;
+ SVGA3dBox boxDest;
+ SVGA3dStretchBltMode mode;
+} SVGA3dCmdSurfaceStretchBlt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 discard : 1;
+
+ uint32 unsynchronized : 1;
+
+ uint32 reserved : 30;
+} SVGA3dSurfaceDMAFlags;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAGuestImage guest;
+ SVGA3dSurfaceImageId host;
+ SVGA3dTransferType transfer;
+
+} SVGA3dCmdSurfaceDMA;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 suffixSize;
+
+ uint32 maximumOffset;
+
+ SVGA3dSurfaceDMAFlags flags;
+} SVGA3dCmdSurfaceDMASuffix;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 first;
+ uint32 last;
+} SVGA3dArrayRangeHint;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 surfaceId;
+ uint32 offset;
+ uint32 stride;
+} SVGA3dArray;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dDeclType type;
+ SVGA3dDeclMethod method;
+ SVGA3dDeclUsage usage;
+ uint32 usageIndex;
+} SVGA3dVertexArrayIdentity;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dVertexDecl {
+ SVGA3dVertexArrayIdentity identity;
+ SVGA3dArray array;
+ SVGA3dArrayRangeHint rangeHint;
+} SVGA3dVertexDecl;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dPrimitiveRange {
+ SVGA3dPrimitiveType primType;
+ uint32 primitiveCount;
+
+ SVGA3dArray indexArray;
+ uint32 indexWidth;
+
+ int32 indexBias;
+} SVGA3dPrimitiveRange;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 numVertexDecls;
+ uint32 numRanges;
+
+} SVGA3dCmdDrawPrimitives;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+ uint32 primitiveCount;
+ uint32 startVertexLocation;
+
+ uint8 primitiveType;
+ uint8 padding[3];
+} SVGA3dCmdDraw;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+ uint8 primitiveType;
+
+ uint32 indexBufferSid;
+ uint32 indexBufferOffset;
+
+ uint8 indexBufferStride;
+
+ int32 baseVertexLocation;
+
+ uint32 primitiveCount;
+ uint32 pad0;
+ uint16 pad1;
+} SVGA3dCmdDrawIndexed;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint16 streamOffset;
+ uint8 stream;
+ uint8 type;
+ uint8 method;
+ uint8 usage;
+ uint8 usageIndex;
+ uint8 padding;
+
+} SVGA3dVertexElement;
+#pragma pack(pop)
-/*
- * Perform a surface copy within the same image.
- * The src/dest boxes are allowed to overlap.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId surface;
- SVGA3dCopyBox box;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdIntraSurfaceCopy; /* SVGA_3D_CMD_INTRA_SURFACE_COPY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 srcSid;
- uint32 destSid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dest;
- SVGA3dBox boxSrc;
- SVGA3dBox boxDest;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSurfaceStretchBltNonMSToMS;
-/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dest;
- SVGA3dBox boxSrc;
- SVGA3dBox boxDest;
- SVGA3dStretchBltMode mode;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- /*
- * If the discard flag is present in a surface DMA operation, the host may
- * discard the contents of the current mipmap level and face of the target
- * surface before applying the surface DMA contents.
- */
- uint32 discard : 1;
-
- /*
- * If the unsynchronized flag is present, the host may perform this upload
- * without syncing to pending reads on this surface.
- */
- uint32 unsynchronized : 1;
-
- /*
- * Guests *MUST* set the reserved bits to 0 before submitting the command
- * suffix as future flags may occupy these bits.
- */
- uint32 reserved : 30;
-}
-#include "vmware_pack_end.h"
-SVGA3dSurfaceDMAFlags;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAGuestImage guest;
- SVGA3dSurfaceImageId host;
- SVGA3dTransferType transfer;
-
- /*
- * Followed by variable number of SVGA3dCopyBox structures. For consistency
- * in all clipping logic and coordinate translation, we define the
- * "source" in each copyBox as the guest image and the
- * "destination" as the host image, regardless of transfer
- * direction.
- *
- * For efficiency, the SVGA3D device is free to copy more data than
- * specified. For example, it may round copy boxes outwards such
- * that they lie on particular alignment boundaries.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
-
-/*
- * SVGA3dCmdSurfaceDMASuffix --
- *
- * This is a command suffix that will appear after a SurfaceDMA command in
- * the FIFO. It contains some extra information that hosts may use to
- * optimize performance or protect the guest. This suffix exists to preserve
- * backwards compatibility while also allowing for new functionality to be
- * implemented.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 suffixSize;
-
- /*
- * The maximum offset is used to determine the maximum offset from the
- * guestPtr base address that will be accessed or written to during this
- * surfaceDMA. If the suffix is supported, the host will respect this
- * boundary while performing surface DMAs.
- *
- * Defaults to MAX_UINT32
- */
- uint32 maximumOffset;
-
- /*
- * A set of flags that describes optimizations that the host may perform
- * while performing this surface DMA operation. The guest should never rely
- * on behaviour that is different when these flags are set for correctness.
- *
- * Defaults to 0
- */
- SVGA3dSurfaceDMAFlags flags;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSurfaceDMASuffix;
-
-/*
- * SVGA_3D_CMD_DRAW_PRIMITIVES --
- *
- * This command is the SVGA3D device's generic drawing entry point.
- * It can draw multiple ranges of primitives, optionally using an
- * index buffer, using an arbitrary collection of vertex buffers.
- *
- * Each SVGA3dVertexDecl defines a distinct vertex array to bind
- * during this draw call. The declarations specify which surface
- * the vertex data lives in, what that vertex data is used for,
- * and how to interpret it.
- *
- * Each SVGA3dPrimitiveRange defines a collection of primitives
- * to render using the same vertex arrays. An index buffer is
- * optional.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- /*
- * A range hint is an optional specification for the range of indices
- * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
- * that the entire array will be used.
- *
- * These are only hints. The SVGA3D device may use them for
- * performance optimization if possible, but it's also allowed to
- * ignore these values.
- */
- uint32 first;
- uint32 last;
-}
-#include "vmware_pack_end.h"
-SVGA3dArrayRangeHint;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- /*
- * Define the origin and shape of a vertex or index array. Both
- * 'offset' and 'stride' are in bytes. The provided surface will be
- * reinterpreted as a flat array of bytes in the same format used
- * by surface DMA operations. To avoid unnecessary conversions, the
- * surface should be created with the SVGA3D_BUFFER format.
- *
- * Index 0 in the array starts 'offset' bytes into the surface.
- * Index 1 begins at byte 'offset + stride', etc. Array indices may
- * not be negative.
- */
- uint32 surfaceId;
- uint32 offset;
- uint32 stride;
-}
-#include "vmware_pack_end.h"
-SVGA3dArray;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- /*
- * Describe a vertex array's data type, and define how it is to be
- * used by the fixed function pipeline or the vertex shader. It
- * isn't useful to have two VertexDecls with the same
- * VertexArrayIdentity in one draw call.
- */
- SVGA3dDeclType type;
- SVGA3dDeclMethod method;
- SVGA3dDeclUsage usage;
- uint32 usageIndex;
-}
-#include "vmware_pack_end.h"
-SVGA3dVertexArrayIdentity;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dVertexDecl {
- SVGA3dVertexArrayIdentity identity;
- SVGA3dArray array;
- SVGA3dArrayRangeHint rangeHint;
-}
-#include "vmware_pack_end.h"
-SVGA3dVertexDecl;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dPrimitiveRange {
- /*
- * Define a group of primitives to render, from sequential indices.
- *
- * The value of 'primitiveType' and 'primitiveCount' imply the
- * total number of vertices that will be rendered.
- */
- SVGA3dPrimitiveType primType;
- uint32 primitiveCount;
-
- /*
- * Optional index buffer. If indexArray.surfaceId is
- * SVGA3D_INVALID_ID, we render without an index buffer. Rendering
- * without an index buffer is identical to rendering with an index
- * buffer containing the sequence [0, 1, 2, 3, ...].
- *
- * If an index buffer is in use, indexWidth specifies the width in
- * bytes of each index value. It must be less than or equal to
- * indexArray.stride.
- *
- * (Currently, the SVGA3D device requires index buffers to be tightly
- * packed. In other words, indexWidth == indexArray.stride)
- */
- SVGA3dArray indexArray;
- uint32 indexWidth;
-
- /*
- * Optional index bias. This number is added to all indices from
- * indexArray before they are used as vertex array indices. This
- * can be used in multiple ways:
- *
- * - When not using an indexArray, this bias can be used to
- * specify where in the vertex arrays to begin rendering.
- *
- * - A positive number here is equivalent to increasing the
- * offset in each vertex array.
- *
- * - A negative number can be used to render using a small
- * vertex array and an index buffer that contains large
- * values. This may be used by some applications that
- * crop a vertex buffer without modifying their index
- * buffer.
- *
- * Note that rendering with a negative bias value may be slower and
- * use more memory than rendering with a positive or zero bias.
- */
- int32 indexBias;
-}
-#include "vmware_pack_end.h"
-SVGA3dPrimitiveRange;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 numVertexDecls;
- uint32 numRanges;
-
- /*
- * There are two variable size arrays after the
- * SVGA3dCmdDrawPrimitives structure. In order,
- * they are:
- *
- * 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
- * SVGA3D_MAX_VERTEX_ARRAYS;
- * 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
- * SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
- * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
- * the frequency divisor for the corresponding vertex decl).
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-
- uint32 primitiveCount; /* How many primitives to render */
- uint32 startVertexLocation; /* Which vertex do we start rendering at. */
-
- uint8 primitiveType; /* SVGA3dPrimitiveType */
- uint8 padding[3];
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDraw;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-
- uint8 primitiveType; /* SVGA3dPrimitiveType */
-
- uint32 indexBufferSid; /* Valid index buffer sid. */
- uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
- /* always 0 for pre SM guests, non-zero for OpenGL */
- /* guests. We can't represent non-multiple of */
- /* stride offsets in D3D9Renderer... */
- uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
-
- int32 baseVertexLocation; /* Bias applied to the index when selecting a */
- /* vertex from the streams, may be negative */
-
- uint32 primitiveCount; /* How many primitives to render */
- uint32 pad0;
- uint16 pad1;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDrawIndexed;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- /*
- * Describe a vertex array's data type, and define how it is to be
- * used by the fixed function pipeline or the vertex shader. It
- * isn't useful to have two VertexDecls with the same
- * VertexArrayIdentity in one draw call.
- */
- uint16 streamOffset;
- uint8 stream;
- uint8 type; /* SVGA3dDeclType */
- uint8 method; /* SVGA3dDeclMethod */
- uint8 usage; /* SVGA3dDeclUsage */
- uint8 usageIndex;
- uint8 padding;
-
-}
-#include "vmware_pack_end.h"
-SVGA3dVertexElement;
-
-/*
- * Should the vertex element respect the stream value? The high bit of the
- * stream should be set to indicate that the stream should be respected. If
- * the high bit is not set, the stream will be ignored and replaced by the index
- * of the position of the currently considered vertex element.
- *
- * All guests should set this bit and correctly specify the stream going
- * forward.
- */
#define SVGA3D_VERTEX_ELEMENT_RESPECT_STREAM (1 << 7)
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-
- uint32 numElements;
-
- /*
- * Followed by numElements SVGA3dVertexElement structures.
- *
- * If numElements < SVGA3D_MAX_VERTEX_ARRAYS, the remaining elements
- * are cleared and will not be used by following draws.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetVertexDecls;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- uint32 stride;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dVertexStream;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
-
- uint32 numStreams;
- /*
- * Followed by numStream SVGA3dVertexStream structures.
- *
- * If numStreams < SVGA3D_MAX_VERTEX_ARRAYS, the remaining streams
- * are cleared and will not be used by following draws.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetVertexStreams;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 numDivisors;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetVertexDivisors;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stage;
- SVGA3dTextureStateName name;
- union {
- uint32 value;
- float floatValue;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dTextureState;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- /* Followed by variable number of SVGA3dTextureState structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dTransformType type;
- float matrix[16];
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- float min;
- float max;
-}
-#include "vmware_pack_end.h"
-SVGA3dZRange;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dZRange zRange;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- float diffuse[4];
- float ambient[4];
- float specular[4];
- float emissive[4];
- float shininess;
-}
-#include "vmware_pack_end.h"
-SVGA3dMaterial;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dFace face;
- SVGA3dMaterial material;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 index;
- SVGA3dLightData data;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 index;
- uint32 enabled;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dRect rect;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dRect rect;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 index;
- float plane[4];
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 shid;
- SVGA3dShaderType type;
- /* Followed by variable number of DWORDs for shader bycode */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 shid;
- SVGA3dShaderType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 reg; /* register number */
- SVGA3dShaderType type;
- SVGA3dShaderConstType ctype;
- uint32 values[4];
-
- /*
- * Followed by a variable number of additional values.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dShaderType type;
- uint32 shid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dQueryType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dQueryType type;
- SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
-
-
-/*
- * SVGA3D_CMD_WAIT_FOR_QUERY --
- *
- * Will read the SVGA3dQueryResult structure pointed to by guestResult,
- * and if the state member is set to anything else than
- * SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op.
- *
- * Otherwise, in addition to the query explicitly waited for,
- * All queries with the same type and issued with the same cid, for which
- * an SVGA_3D_CMD_END_QUERY command has previously been sent, will
- * be finished after execution of this command.
- *
- * A query will be identified by the gmrId and offset of the guestResult
- * member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
- * been sent previously with an indentical gmrId and offset, it will
- * effectively end all queries with an identical type issued with the
- * same cid, and the SVGA3dQueryResult structure pointed to by
- * guestResult will not be written to. This property can be used to
- * implement a query barrier for a given cid and query type.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid; /* Same parameters passed to END_QUERY */
- SVGA3dQueryType type;
- SVGAGuestPtr guestResult;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 totalSize; /* Set by guest before query is ended. */
- SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
- union { /* Set by host on exit from PENDING state */
- uint32 result32;
- uint32 queryCookie; /* May be used to identify which QueryGetData this
- result corresponds to. */
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dQueryResult;
-
-
-/*
- * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
- *
- * This is a blit from an SVGA3D surface to a Screen Object.
- * This blit must be directed at a specific screen.
- *
- * The blit copies from a rectangular region of an SVGA3D surface
- * image to a rectangular region of a screen.
- *
- * This command takes an optional variable-length list of clipping
- * rectangles after the body of the command. If no rectangles are
- * specified, there is no clipping region. The entire destRect is
- * drawn to. If one or more rectangles are included, they describe
- * a clipping region. The clip rectangle coordinates are measured
- * relative to the top-left corner of destRect.
- *
- * The srcImage must be from mip=0 face=0.
- *
- * This supports scaling if the src and dest are of different sizes.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId srcImage;
- SVGASignedRect srcRect;
- uint32 destScreenId; /* Screen Object ID */
- SVGASignedRect destRect;
- /* Clipping: zero or more SVGASignedRects follow */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- SVGA3dTextureFilter filter;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */
-
-/*
- * Screen DMA command
- *
- * Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device
- * cap bit is not required.
- *
- * - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could
- * be different, but it is required that guest makes sure refBuffer has
- * exactly the same contents that were written to when last time screen DMA
- * command is received by host.
- *
- * - changemap is generated by lib/blit, and it has the changes from last
- * received screen DMA or more.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdScreenDMA {
- uint32 screenId;
- SVGAGuestImage refBuffer;
- SVGAGuestImage destBuffer;
- SVGAGuestImage changeMap;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
-
-/*
- * Logic ops
- */
-
-#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
-#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
-#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
-#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsBitBlt {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dst;
- SVGA3dLogicOp logicOp;
- SVGA3dLogicOpRop3 logicOpRop3;
- /* Followed by variable number of SVGA3dCopyBox structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsTransBlt {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dst;
- uint32 color;
- uint32 flags;
- SVGA3dBox srcBox;
- SVGA3dSignedBox dstBox;
- SVGA3dBox clipBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsStretchBlt {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dst;
- uint16 mode;
- uint16 flags;
- SVGA3dBox srcBox;
- SVGA3dSignedBox dstBox;
- SVGA3dBox clipBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsColorFill {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId dst;
- uint32 color;
- SVGA3dLogicOp logicOp;
- SVGA3dLogicOpRop3 logicOpRop3;
- /* Followed by variable number of SVGA3dRect structures. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsAlphaBlend {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId src;
- SVGA3dSurfaceImageId dst;
- uint32 alphaVal;
- uint32 flags;
- SVGA3dBox srcBox;
- SVGA3dSignedBox dstBox;
- SVGA3dBox clipBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+ uint32 numElements;
+
+} SVGA3dCmdSetVertexDecls;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+ uint32 stride;
+ uint32 offset;
+} SVGA3dVertexStream;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+ uint32 numStreams;
+
+} SVGA3dCmdSetVertexStreams;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 numDivisors;
+} SVGA3dCmdSetVertexDivisors;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stage;
+ SVGA3dTextureStateName name;
+ union {
+ uint32 value;
+ float floatValue;
+ };
+} SVGA3dTextureState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+
+} SVGA3dCmdSetTextureState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dTransformType type;
+ float matrix[16];
+} SVGA3dCmdSetTransform;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ float min;
+ float max;
+} SVGA3dZRange;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dZRange zRange;
+} SVGA3dCmdSetZRange;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ float diffuse[4];
+ float ambient[4];
+ float specular[4];
+ float emissive[4];
+ float shininess;
+} SVGA3dMaterial;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dFace face;
+ SVGA3dMaterial material;
+} SVGA3dCmdSetMaterial;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 index;
+ SVGA3dLightData data;
+} SVGA3dCmdSetLightData;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 index;
+ uint32 enabled;
+} SVGA3dCmdSetLightEnabled;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dRect rect;
+} SVGA3dCmdSetViewport;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dRect rect;
+} SVGA3dCmdSetScissorRect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 index;
+ float plane[4];
+} SVGA3dCmdSetClipPlane;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 shid;
+ SVGA3dShaderType type;
+
+} SVGA3dCmdDefineShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 shid;
+ SVGA3dShaderType type;
+} SVGA3dCmdDestroyShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 reg;
+ SVGA3dShaderType type;
+ SVGA3dShaderConstType ctype;
+ uint32 values[4];
+
+} SVGA3dCmdSetShaderConst;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dShaderType type;
+ uint32 shid;
+} SVGA3dCmdSetShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+} SVGA3dCmdBeginQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+ SVGAGuestPtr guestResult;
+} SVGA3dCmdEndQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+ SVGAGuestPtr guestResult;
+} SVGA3dCmdWaitForQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 totalSize;
+ SVGA3dQueryState state;
+ union {
+ uint32 result32;
+ uint32 queryCookie;
+ };
+} SVGA3dQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId srcImage;
+ SVGASignedRect srcRect;
+ uint32 destScreenId;
+ SVGASignedRect destRect;
+
+} SVGA3dCmdBlitSurfaceToScreen;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+ SVGA3dTextureFilter filter;
+} SVGA3dCmdGenerateMipmaps;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+} SVGA3dCmdActivateSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+} SVGA3dCmdDeactivateSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdScreenDMA {
+ uint32 screenId;
+ SVGAGuestImage refBuffer;
+ SVGAGuestImage destBuffer;
+ SVGAGuestImage changeMap;
+} SVGA3dCmdScreenDMA;
+#pragma pack(pop)
+
+#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
+#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
+#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
+#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsBitBlt {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dst;
+ SVGA3dLogicOp logicOp;
+ SVGA3dLogicOpRop3 logicOpRop3;
+
+} SVGA3dCmdLogicOpsBitBlt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsTransBlt {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dst;
+ uint32 color;
+ uint32 flags;
+ SVGA3dBox srcBox;
+ SVGA3dSignedBox dstBox;
+ SVGA3dBox clipBox;
+} SVGA3dCmdLogicOpsTransBlt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsStretchBlt {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dst;
+ uint16 mode;
+ uint16 flags;
+ SVGA3dBox srcBox;
+ SVGA3dSignedBox dstBox;
+ SVGA3dBox clipBox;
+} SVGA3dCmdLogicOpsStretchBlt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsColorFill {
+ SVGA3dSurfaceImageId dst;
+ uint32 color;
+ SVGA3dLogicOp logicOp;
+ SVGA3dLogicOpRop3 logicOpRop3;
+
+} SVGA3dCmdLogicOpsColorFill;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsAlphaBlend {
+ SVGA3dSurfaceImageId src;
+ SVGA3dSurfaceImageId dst;
+ uint32 alphaVal;
+ uint32 flags;
+ SVGA3dBox srcBox;
+ SVGA3dSignedBox dstBox;
+ SVGA3dBox clipBox;
+} SVGA3dCmdLogicOpsAlphaBlend;
+#pragma pack(pop)
#define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF
-#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
+#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
#define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdLogicOpsClearTypeBlend {
- /*
- * All LogicOps surfaces are one-level
- * surfaces so mipmap & face should always
- * be zero.
- */
- SVGA3dSurfaceImageId tmp;
- SVGA3dSurfaceImageId dst;
- SVGA3dSurfaceImageId gammaSurf;
- SVGA3dSurfaceImageId alphaSurf;
- uint32 gamma;
- uint32 color;
- uint32 color2;
- int32 alphaOffsetX;
- int32 alphaOffsetY;
- /* Followed by variable number of SVGA3dBox structures */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
-
-
-/*
- * Guest-backed objects definitions.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAMobFormat ptDepth;
- uint32 sizeInBytes;
- PPN64 base;
-}
-#include "vmware_pack_end.h"
-SVGAOTableMobEntry;
-#define SVGA3D_OTABLE_MOB_ENTRY_SIZE (sizeof(SVGAOTableMobEntry))
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceFormat format;
- SVGA3dSurface1Flags surface1Flags;
- uint32 numMipLevels;
- uint32 multisampleCount;
- SVGA3dTextureFilter autogenFilter;
- SVGA3dSize size;
- SVGAMobId mobid;
- uint32 arraySize;
- uint32 mobPitch;
- SVGA3dSurface2Flags surface2Flags;
- uint8 multisamplePattern;
- uint8 qualityLevel;
- uint16 bufferByteStride;
- float minLOD;
- uint32 pad0[2];
-}
-#include "vmware_pack_end.h"
-SVGAOTableSurfaceEntry;
-#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE (sizeof(SVGAOTableSurfaceEntry))
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGAOTableContextEntry;
-#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE (sizeof(SVGAOTableContextEntry))
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dShaderType type;
- uint32 sizeInBytes;
- uint32 offsetInBytes;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGAOTableShaderEntry;
-#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
-
-#define SVGA_STFLAG_PRIMARY (1 << 0)
-#define SVGA_STFLAG_RESERVED (1 << 1) /* Added with cap SVGA_CAP_HP_CMD_QUEUE */
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdLogicOpsClearTypeBlend {
+ SVGA3dSurfaceImageId tmp;
+ SVGA3dSurfaceImageId dst;
+ SVGA3dSurfaceImageId gammaSurf;
+ SVGA3dSurfaceImageId alphaSurf;
+ uint32 gamma;
+ uint32 color;
+ uint32 color2;
+ int32 alphaOffsetX;
+ int32 alphaOffsetY;
+
+} SVGA3dCmdLogicOpsClearTypeBlend;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAMobFormat ptDepth;
+ uint32 sizeInBytes;
+ PPN64 base;
+} SVGAOTableMobEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceFormat format;
+ SVGA3dSurface1Flags surface1Flags;
+ uint32 numMipLevels;
+ uint32 multisampleCount;
+ SVGA3dTextureFilter autogenFilter;
+ SVGA3dSize size;
+ SVGAMobId mobid;
+ uint32 arraySize;
+ uint32 mobPitch;
+ SVGA3dSurface2Flags surface2Flags;
+ uint8 multisamplePattern;
+ uint8 qualityLevel;
+ uint16 bufferByteStride;
+ float minLOD;
+ uint32 pad0[2];
+} SVGAOTableSurfaceEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGAMobId mobid;
+} SVGAOTableContextEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dShaderType type;
+ uint32 sizeInBytes;
+ uint32 offsetInBytes;
+ SVGAMobId mobid;
+} SVGAOTableShaderEntry;
+#pragma pack(pop)
+
+#define SVGA_STFLAG_PRIMARY (1 << 0)
+#define SVGA_STFLAG_RESERVED (1 << 1)
typedef uint32 SVGAScreenTargetFlags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceImageId image;
- uint32 width;
- uint32 height;
- int32 xRoot;
- int32 yRoot;
- SVGAScreenTargetFlags flags;
- uint32 dpi;
- uint32 pad[7];
-}
-#include "vmware_pack_end.h"
-SVGAOTableScreenTargetEntry;
-#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE \
- (sizeof(SVGAOTableScreenTargetEntry))
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- float value[4];
-}
-#include "vmware_pack_end.h"
-SVGA3dShaderConstFloat;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- int32 value[4];
-}
-#include "vmware_pack_end.h"
-SVGA3dShaderConstInt;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 value;
-}
-#include "vmware_pack_end.h"
-SVGA3dShaderConstBool;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint16 streamOffset;
- uint8 stream;
- uint8 type;
- uint8 methodUsage;
- uint8 usageIndex;
-}
-#include "vmware_pack_end.h"
-SVGAGBVertexElement;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
- uint16 stride;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGAGBVertexStream;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dRect viewport;
- SVGA3dRect scissorRect;
- SVGA3dZRange zRange;
-
- SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
- SVGAGBVertexElement decl1[4];
-
- uint32 renderStates[SVGA3D_RS_MAX];
- SVGAGBVertexElement decl2[18];
- uint32 pad0[2];
-
- struct {
- SVGA3dFace face;
- SVGA3dMaterial material;
- } material;
-
- float clipPlanes[SVGA3D_NUM_CLIPPLANES][4];
- float matrices[SVGA3D_TRANSFORM_MAX][16];
-
- SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
- SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
-
- /*
- * Shaders currently bound
- */
- uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
- SVGAGBVertexElement decl3[10];
- uint32 pad1[3];
-
- uint32 occQueryActive;
- uint32 occQueryValue;
-
- /*
- * Int/Bool Shader constants
- */
- SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
- SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
- uint16 pShaderBValues;
- uint16 vShaderBValues;
-
-
- SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
- SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
- uint32 numVertexDecls;
- uint32 numVertexStreams;
- uint32 numVertexDivisors;
- uint32 pad2[30];
-
- /*
- * Texture Stages
- *
- * SVGA3D_TS_INVALID through SVGA3D_TS_CONSTANT are in the
- * textureStages array.
- * SVGA3D_TS_COLOR_KEY is in tsColorKey.
- */
- uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
- uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
- uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
-
- /*
- * Float Shader constants.
- */
- SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
- SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
-}
-#include "vmware_pack_end.h"
-SVGAGBContextData;
-#define SVGA3D_CONTEXT_DATA_SIZE (sizeof(SVGAGBContextData))
-
-/*
- * SVGA3dCmdSetOTableBase --
- *
- * This command allows the guest to specify the base PPN of the
- * specified object table.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAOTableType type;
- PPN32 baseAddress;
- uint32 sizeInBytes;
- uint32 validSizeInBytes;
- SVGAMobFormat ptDepth;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAOTableType type;
- PPN64 baseAddress;
- uint32 sizeInBytes;
- uint32 validSizeInBytes;
- SVGAMobFormat ptDepth;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
-
-/*
- * Guests using SVGA_3D_CMD_GROW_OTABLE are promising that
- * the new OTable contains the same contents as the old one, except possibly
- * for some new invalid entries at the end.
- *
- * (Otherwise, guests should use one of the SetOTableBase commands.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAOTableType type;
- PPN64 baseAddress;
- uint32 sizeInBytes;
- uint32 validSizeInBytes;
- SVGAMobFormat ptDepth;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdGrowOTable; /* SVGA_3D_CMD_GROW_OTABLE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAOTableType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
-
-/*
- * Define a memory object (Mob) in the OTable.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBMob {
- SVGAMobId mobid;
- SVGAMobFormat ptDepth;
- PPN32 base;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
-
-
-/*
- * Destroys an object in the OTable.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDestroyGBMob {
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
-
-/*
- * Define a memory object (Mob) in the OTable with a PPN64 base.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBMob64 {
- SVGAMobId mobid;
- SVGAMobFormat ptDepth;
- PPN64 base;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
-
-/*
- * Redefine an object in the OTable with PPN64 base.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdRedefineGBMob64 {
- SVGAMobId mobid;
- SVGAMobFormat ptDepth;
- PPN64 base;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
-
-/*
- * Notification that the page tables have been modified.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdUpdateGBMobMapping {
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
-
-/*
- * Define a guest-backed surface.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBSurface {
- uint32 sid;
- SVGA3dSurface1Flags surfaceFlags;
- SVGA3dSurfaceFormat format;
- uint32 numMipLevels;
- uint32 multisampleCount;
- SVGA3dTextureFilter autogenFilter;
- SVGA3dSize size;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
-
-/*
- * Defines a guest-backed surface, adding the arraySize field.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBSurface_v2 {
- uint32 sid;
- SVGA3dSurface1Flags surfaceFlags;
- SVGA3dSurfaceFormat format;
- uint32 numMipLevels;
- uint32 multisampleCount;
- SVGA3dTextureFilter autogenFilter;
- SVGA3dSize size;
- uint32 arraySize;
- uint32 pad;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
-
-/*
- * Defines a guest-backed surface, adding the larger flags.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBSurface_v3 {
- uint32 sid;
- SVGA3dSurfaceAllFlags surfaceFlags;
- SVGA3dSurfaceFormat format;
- uint32 numMipLevels;
- uint32 multisampleCount;
- SVGA3dMSPattern multisamplePattern;
- SVGA3dMSQualityLevel qualityLevel;
- SVGA3dTextureFilter autogenFilter;
- SVGA3dSize size;
- uint32 arraySize;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */
-
-/*
- * Defines a guest-backed surface, adding buffer byte stride.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBSurface_v4 {
- uint32 sid;
- SVGA3dSurfaceAllFlags surfaceFlags;
- SVGA3dSurfaceFormat format;
- uint32 numMipLevels;
- uint32 multisampleCount;
- SVGA3dMSPattern multisamplePattern;
- SVGA3dMSQualityLevel qualityLevel;
- SVGA3dTextureFilter autogenFilter;
- SVGA3dSize size;
- uint32 arraySize;
- uint32 bufferByteStride;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBSurface_v4; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 */
-
-/*
- * Destroy a guest-backed surface.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDestroyGBSurface {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
-
-/*
- * Bind a guest-backed surface to a mob.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdBindGBSurface {
- uint32 sid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdBindGBSurfaceWithPitch {
- uint32 sid;
- SVGAMobId mobid;
- uint32 baseLevelPitch;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
-
-/*
- * Conditionally bind a mob to a guest-backed surface if testMobid
- * matches the currently bound mob. Optionally issue a
- * readback/update on the surface while it is still bound to the old
- * mobid if the mobid is changed by this command.
- */
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceImageId image;
+ uint32 width;
+ uint32 height;
+ int32 xRoot;
+ int32 yRoot;
+ SVGAScreenTargetFlags flags;
+ uint32 dpi;
+ uint32 pad[7];
+} SVGAOTableScreenTargetEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ float value[4];
+} SVGA3dShaderConstFloat;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ int32 value[4];
+} SVGA3dShaderConstInt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 value;
+} SVGA3dShaderConstBool;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint16 streamOffset;
+ uint8 stream;
+ uint8 type;
+ uint8 methodUsage;
+ uint8 usageIndex;
+} SVGAGBVertexElement;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+ uint16 stride;
+ uint32 offset;
+} SVGAGBVertexStream;
+#pragma pack(pop)
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dRect viewport;
+ SVGA3dRect scissorRect;
+ SVGA3dZRange zRange;
+
+ SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
+ SVGAGBVertexElement decl1[4];
+
+ uint32 renderStates[SVGA3D_RS_MAX];
+ SVGAGBVertexElement decl2[18];
+ uint32 pad0[2];
+
+ struct {
+ SVGA3dFace face;
+ SVGA3dMaterial material;
+ } material;
+
+ float clipPlanes[SVGA3D_MAX_CLIP_PLANES][4];
+ float matrices[SVGA3D_TRANSFORM_MAX][16];
+
+ SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
+ SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
+
+ uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
+ SVGAGBVertexElement decl3[10];
+ uint32 pad1[3];
+
+ uint32 occQueryActive;
+ uint32 occQueryValue;
+
+ SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
+ SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
+ uint16 pShaderBValues;
+ uint16 vShaderBValues;
+
+ SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
+ SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
+ uint32 numVertexDecls;
+ uint32 numVertexStreams;
+ uint32 numVertexDivisors;
+ uint32 pad2[30];
+
+ uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
+ uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
+ uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
+
+ SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
+ SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
+} SVGAGBContextData;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAOTableType type;
+ PPN32 baseAddress;
+ uint32 sizeInBytes;
+ uint32 validSizeInBytes;
+ SVGAMobFormat ptDepth;
+} SVGA3dCmdSetOTableBase;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAOTableType type;
+ PPN64 baseAddress;
+ uint32 sizeInBytes;
+ uint32 validSizeInBytes;
+ SVGAMobFormat ptDepth;
+} SVGA3dCmdSetOTableBase64;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAOTableType type;
+ PPN64 baseAddress;
+ uint32 sizeInBytes;
+ uint32 validSizeInBytes;
+ SVGAMobFormat ptDepth;
+} SVGA3dCmdGrowOTable;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAOTableType type;
+} SVGA3dCmdReadbackOTable;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBMob {
+ SVGAMobId mobid;
+ SVGAMobFormat ptDepth;
+ PPN32 base;
+ uint32 sizeInBytes;
+} SVGA3dCmdDefineGBMob;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDestroyGBMob {
+ SVGAMobId mobid;
+} SVGA3dCmdDestroyGBMob;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBMob64 {
+ SVGAMobId mobid;
+ SVGAMobFormat ptDepth;
+ PPN64 base;
+ uint32 sizeInBytes;
+} SVGA3dCmdDefineGBMob64;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdRedefineGBMob64 {
+ SVGAMobId mobid;
+ SVGAMobFormat ptDepth;
+ PPN64 base;
+ uint32 sizeInBytes;
+} SVGA3dCmdRedefineGBMob64;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdUpdateGBMobMapping {
+ SVGAMobId mobid;
+} SVGA3dCmdUpdateGBMobMapping;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBSurface {
+ uint32 sid;
+ SVGA3dSurface1Flags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+ uint32 numMipLevels;
+ uint32 multisampleCount;
+ SVGA3dTextureFilter autogenFilter;
+ SVGA3dSize size;
+} SVGA3dCmdDefineGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBSurface_v2 {
+ uint32 sid;
+ SVGA3dSurface1Flags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+ uint32 numMipLevels;
+ uint32 multisampleCount;
+ SVGA3dTextureFilter autogenFilter;
+ SVGA3dSize size;
+ uint32 arraySize;
+ uint32 pad;
+} SVGA3dCmdDefineGBSurface_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBSurface_v3 {
+ uint32 sid;
+ SVGA3dSurfaceAllFlags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+ uint32 numMipLevels;
+ uint32 multisampleCount;
+ SVGA3dMSPattern multisamplePattern;
+ SVGA3dMSQualityLevel qualityLevel;
+ SVGA3dTextureFilter autogenFilter;
+ SVGA3dSize size;
+ uint32 arraySize;
+} SVGA3dCmdDefineGBSurface_v3;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBSurface_v4 {
+ uint32 sid;
+ SVGA3dSurfaceAllFlags surfaceFlags;
+ SVGA3dSurfaceFormat format;
+ uint32 numMipLevels;
+ uint32 multisampleCount;
+ SVGA3dMSPattern multisamplePattern;
+ SVGA3dMSQualityLevel qualityLevel;
+ SVGA3dTextureFilter autogenFilter;
+ SVGA3dSize size;
+ uint32 arraySize;
+ uint32 bufferByteStride;
+} SVGA3dCmdDefineGBSurface_v4;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDestroyGBSurface {
+ uint32 sid;
+} SVGA3dCmdDestroyGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdBindGBSurface {
+ uint32 sid;
+ SVGAMobId mobid;
+} SVGA3dCmdBindGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdBindGBSurfaceWithPitch {
+ uint32 sid;
+ SVGAMobId mobid;
+ uint32 baseLevelPitch;
+} SVGA3dCmdBindGBSurfaceWithPitch;
+#pragma pack(pop)
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
-#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdCondBindGBSurface {
- uint32 sid;
- SVGAMobId testMobid;
- SVGAMobId mobid;
- uint32 flags;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
-
-/*
- * Update an image in a guest-backed surface.
- * (Inform the device that the guest-contents have been updated.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdUpdateGBImage {
- SVGA3dSurfaceImageId image;
- SVGA3dBox box;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
-
-/*
- * Update an entire guest-backed surface.
- * (Inform the device that the guest-contents have been updated.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdUpdateGBSurface {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
-
-/*
- * Readback an image in a guest-backed surface.
- * (Request the device to flush the dirty contents into the guest.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdReadbackGBImage {
- SVGA3dSurfaceImageId image;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */
-
-/*
- * Readback an entire guest-backed surface.
- * (Request the device to flush the dirty contents into the guest.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdReadbackGBSurface {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
-
-/*
- * Readback a sub rect of an image in a guest-backed surface. After
- * issuing this command the driver is required to issue an update call
- * of the same region before issuing any other commands that reference
- * this surface or rendering is not guaranteed.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdReadbackGBImagePartial {
- SVGA3dSurfaceImageId image;
- SVGA3dBox box;
- uint32 invertBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
-
-
-/*
- * Invalidate an image in a guest-backed surface.
- * (Notify the device that the contents can be lost.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdInvalidateGBImage {
- SVGA3dSurfaceImageId image;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
-
-/*
- * Invalidate an entire guest-backed surface.
- * (Notify the device that the contents if all images can be lost.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdInvalidateGBSurface {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
-
-/*
- * Invalidate a sub rect of an image in a guest-backed surface. After
- * issuing this command the driver is required to issue an update call
- * of the same region before issuing any other commands that reference
- * this surface or rendering is not guaranteed.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdInvalidateGBImagePartial {
- SVGA3dSurfaceImageId image;
- SVGA3dBox box;
- uint32 invertBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
-
-
-/*
- * Define a guest-backed context.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
-
-/*
- * Destroy a guest-backed context.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDestroyGBContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
-
-/*
- * Bind a guest-backed context.
- *
- * validContents should be set to 0 for new contexts,
- * and 1 if this is an old context which is getting paged
- * back on to the device.
- *
- * For new contexts, it is recommended that the driver
- * issue commands to initialize all interesting state
- * prior to rendering.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdBindGBContext {
- uint32 cid;
- SVGAMobId mobid;
- uint32 validContents;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
-
-/*
- * Readback a guest-backed context.
- * (Request that the device flush the contents back into guest memory.)
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdReadbackGBContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
-
-/*
- * Invalidate a guest-backed context.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdInvalidateGBContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
-
-/*
- * Define a guest-backed shader.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDefineGBShader {
- uint32 shid;
- SVGA3dShaderType type;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
-
-/*
- * Bind a guest-backed shader.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdBindGBShader {
- uint32 shid;
- SVGAMobId mobid;
- uint32 offsetInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
-
-/*
- * Destroy a guest-backed shader.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDestroyGBShader {
- uint32 shid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- uint32 regStart;
- SVGA3dShaderType shaderType;
- SVGA3dShaderConstType constType;
-
- /*
- * Followed by a variable number of shader constants.
- *
- * Note that FLOAT and INT constants are 4-dwords in length, while
- * BOOL constants are 1-dword in length.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dQueryType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dQueryType type;
- SVGAMobId mobid;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
-
-
-/*
- * SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
- *
- * The semantics of this command are identical to the
- * SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
- * to a Mob instead of a GMR.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGA3dQueryType type;
- SVGAMobId mobid;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAMobId mobid;
- uint32 mustBeZero;
- uint32 initialized;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAMobId mobid;
- uint32 gartOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 gartOffset;
- uint32 numPages;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
-
-
-/*
- * Screen Targets
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stid;
- uint32 width;
- uint32 height;
- int32 xRoot;
- int32 yRoot;
- SVGAScreenTargetFlags flags;
-
- /*
- * The physical DPI that the guest expects this screen displayed at.
- *
- * Guests which are not DPI-aware should set this to zero.
- */
- uint32 dpi;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stid;
- SVGA3dSurfaceImageId image;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stid;
- SVGA3dRect rect;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdGBScreenDMA {
- uint32 screenId;
- uint32 dead;
- SVGAMobId destMobID;
- uint32 destPitch;
- SVGAMobId changeMapMobID;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 value;
- uint32 mobId;
- uint32 mobOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 stid;
- SVGA3dSurfaceImageId dest;
-
- uint32 statusMobId;
- uint32 statusMobOffset;
-
- /* Reserved fields */
- uint32 mustBeInvalidId;
- uint32 mustBeZero;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
+#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdCondBindGBSurface {
+ uint32 sid;
+ SVGAMobId testMobid;
+ SVGAMobId mobid;
+ uint32 flags;
+} SVGA3dCmdCondBindGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdUpdateGBImage {
+ SVGA3dSurfaceImageId image;
+ SVGA3dBox box;
+} SVGA3dCmdUpdateGBImage;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdUpdateGBSurface {
+ uint32 sid;
+} SVGA3dCmdUpdateGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdReadbackGBImage {
+ SVGA3dSurfaceImageId image;
+} SVGA3dCmdReadbackGBImage;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdReadbackGBSurface {
+ uint32 sid;
+} SVGA3dCmdReadbackGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdReadbackGBImagePartial {
+ SVGA3dSurfaceImageId image;
+ SVGA3dBox box;
+ uint32 invertBox;
+} SVGA3dCmdReadbackGBImagePartial;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdInvalidateGBImage {
+ SVGA3dSurfaceImageId image;
+} SVGA3dCmdInvalidateGBImage;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdInvalidateGBSurface {
+ uint32 sid;
+} SVGA3dCmdInvalidateGBSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdInvalidateGBImagePartial {
+ SVGA3dSurfaceImageId image;
+ SVGA3dBox box;
+ uint32 invertBox;
+} SVGA3dCmdInvalidateGBImagePartial;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBContext {
+ uint32 cid;
+} SVGA3dCmdDefineGBContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDestroyGBContext {
+ uint32 cid;
+} SVGA3dCmdDestroyGBContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdBindGBContext {
+ uint32 cid;
+ SVGAMobId mobid;
+ uint32 validContents;
+} SVGA3dCmdBindGBContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdReadbackGBContext {
+ uint32 cid;
+} SVGA3dCmdReadbackGBContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdInvalidateGBContext {
+ uint32 cid;
+} SVGA3dCmdInvalidateGBContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDefineGBShader {
+ uint32 shid;
+ SVGA3dShaderType type;
+ uint32 sizeInBytes;
+} SVGA3dCmdDefineGBShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdBindGBShader {
+ uint32 shid;
+ SVGAMobId mobid;
+ uint32 offsetInBytes;
+} SVGA3dCmdBindGBShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDestroyGBShader {
+ uint32 shid;
+} SVGA3dCmdDestroyGBShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ uint32 regStart;
+ SVGA3dShaderType shaderType;
+ SVGA3dShaderConstType constType;
+
+} SVGA3dCmdSetGBShaderConstInline;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+} SVGA3dCmdBeginGBQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+ SVGAMobId mobid;
+ uint32 offset;
+} SVGA3dCmdEndGBQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGA3dQueryType type;
+ SVGAMobId mobid;
+ uint32 offset;
+} SVGA3dCmdWaitForGBQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAMobId mobid;
+ uint32 mustBeZero;
+ uint32 initialized;
+} SVGA3dCmdEnableGart;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAMobId mobid;
+ uint32 gartOffset;
+} SVGA3dCmdMapMobIntoGart;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 gartOffset;
+ uint32 numPages;
+} SVGA3dCmdUnmapGartRange;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ uint32 width;
+ uint32 height;
+ int32 xRoot;
+ int32 yRoot;
+ SVGAScreenTargetFlags flags;
+
+ uint32 dpi;
+} SVGA3dCmdDefineGBScreenTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+} SVGA3dCmdDestroyGBScreenTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ SVGA3dSurfaceImageId image;
+} SVGA3dCmdBindGBScreenTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ SVGA3dRect rect;
+} SVGA3dCmdUpdateGBScreenTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ SVGA3dRect rect;
+ SVGA3dFrameUpdateType type;
+} SVGA3dCmdUpdateGBScreenTarget_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ SVGA3dRect rect;
+ SVGA3dFrameUpdateType type;
+ SVGAUnsignedPoint srcPoint;
+} SVGA3dCmdUpdateGBScreenTargetMove;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdGBScreenDMA {
+ uint32 screenId;
+ uint32 dead;
+ SVGAMobId destMobID;
+ uint32 destPitch;
+ SVGAMobId changeMapMobID;
+} SVGA3dCmdGBScreenDMA;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 value;
+ uint32 mobId;
+ uint32 mobOffset;
+} SVGA3dCmdGBMobFence;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 stid;
+ SVGA3dSurfaceImageId dest;
+
+ uint32 statusMobId;
+ uint32 statusMobOffset;
+
+ uint32 mustBeInvalidId;
+ uint32 mustBeZero;
+} SVGA3dCmdScreenCopy;
+#pragma pack(pop)
#define SVGA_SCREEN_COPY_STATUS_FAILURE 0x00
#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdWriteZeroSurface; /* SVGA_3D_CMD_WRITE_ZERO_SURFACE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 sid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdHintZeroSurface; /* SVGA_3D_CMD_HINT_ZERO_SURFACE */
-
-#endif /* _SVGA3D_CMD_H_ */
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+} SVGA3dCmdWriteZeroSurface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 sid;
+} SVGA3dCmdUpdateZeroSurface;
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
index 617b468c626c4c82b214bf92f9902fef21007179..379ec15c7758b901826e988c1de512089222d90e 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 1998-2019 VMware, Inc.
+ * Copyright 1998-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,484 +27,345 @@
/*
* svga3d_devcaps.h --
*
- * SVGA 3d caps definitions
+ * SVGA 3d caps definitions
*/
-#ifndef _SVGA3D_DEVCAPS_H_
-#define _SVGA3D_DEVCAPS_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
+#ifndef _SVGA3D_DEVCAPS_H_
+#define _SVGA3D_DEVCAPS_H_
#include "svga3d_types.h"
-/*
- * 3D Hardware Version
- *
- * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
- * register. Is set by the host and read by the guest. This lets
- * us make new guest drivers which are backwards-compatible with old
- * SVGA hardware revisions. It does not let us support old guest
- * drivers. Good enough for now.
- *
- */
-
-#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
-#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
-#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
+#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor)&0xFF))
+#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
+#define SVGA3D_MINOR_HWVERSION(version) ((version)&0xFF)
typedef enum {
- SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
- SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
- SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
- SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
- SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
- SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
- SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
- SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
+ SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
+ SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
+ SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
+ SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
+ SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
+ SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
+ SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
+ SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
} SVGA3dHardwareVersion;
-/*
- * DevCap indexes.
- */
-
typedef uint32 SVGA3dDevCapIndex;
-#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
-#define SVGA3D_DEVCAP_3D 0
-#define SVGA3D_DEVCAP_MAX_LIGHTS 1
-
-/*
- * SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
- * fixed-function texture units available. Each of these units
- * work in both FFP and Shader modes, and they support texture
- * transforms and texture coordinates. The host may have additional
- * texture image units that are only usable with shaders.
- */
-#define SVGA3D_DEVCAP_MAX_TEXTURES 2
-#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
-#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
-#define SVGA3D_DEVCAP_VERTEX_SHADER 5
-#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
-#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
-#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
-#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
-#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
-#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
-#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
-#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
-#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
-#define SVGA3D_DEVCAP_QUERY_TYPES 15
-#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
-#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
-#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
-#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
-#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
-#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
-#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
-#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
-#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
-#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
-#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
-#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
-#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
-#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
-#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
-#define SVGA3D_DEVCAP_TEXTURE_OPS 31
-#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
-#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
-#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
-#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
-#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
-#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
-#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
-#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
-#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
-#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
-#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
-#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
-#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
-#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
-#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
-#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
-#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
-#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
-#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
-#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
-#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
-#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
-#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
-#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
-#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
-#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
-#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
-
-/*
- * There is a hole in our devcap definitions for
- * historical reasons.
- *
- * Define a constant just for completeness.
- */
-#define SVGA3D_DEVCAP_MISSING62 62
-
-#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
-
-/*
- * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
- * render targets. This does not include the depth or stencil targets.
- */
-#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
-
-#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
-#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
-#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
-#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
-#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
-
-/*
- * Deprecated.
- */
-#define SVGA3D_DEVCAP_DEAD4 70
-#define SVGA3D_DEVCAP_DEAD5 71
-#define SVGA3D_DEVCAP_DEAD7 72
-#define SVGA3D_DEVCAP_DEAD6 73
-
-#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
-#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
-#define SVGA3D_DEVCAP_DEAD10 76
-
-/*
- * This is the maximum number of SVGA context IDs that the guest
- * can define using SVGA_3D_CMD_CONTEXT_DEFINE.
- */
-#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
-
-/*
- * This is the maximum number of SVGA surface IDs that the guest
- * can define using SVGA_3D_CMD_SURFACE_DEFINE*.
- */
-#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
-
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
-#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
-
-#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
-#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
-
-/*
- * Deprecated.
- */
-#define SVGA3D_DEVCAP_DEAD1 84
-#define SVGA3D_DEVCAP_DEAD8 85
-#define SVGA3D_DEVCAP_DEAD9 86
-
-#define SVGA3D_DEVCAP_LINE_AA 87 /* boolean */
-#define SVGA3D_DEVCAP_LINE_STIPPLE 88 /* boolean */
-#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89 /* float */
-#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90 /* float */
-
-#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
-
-/*
- * Deprecated.
- */
-#define SVGA3D_DEVCAP_DEAD3 92
-
-/*
- * Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
- */
-#define SVGA3D_DEVCAP_TS_COLOR_KEY 93 /* boolean */
-
-/*
- * Deprecated.
- */
-#define SVGA3D_DEVCAP_DEAD2 94
-
-/*
- * Does the device support DXContexts?
- */
-#define SVGA3D_DEVCAP_DXCONTEXT 95
-
-/*
- * Deprecated.
- */
-#define SVGA3D_DEVCAP_DEAD11 96
-
-/*
- * What is the maximum number of vertex buffers or vertex input registers
- * that can be expected to work correctly with a DXContext?
- *
- * The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
- * anything in excess of this cap is not guaranteed to render correctly.
- *
- * Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
- * input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
- * SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
- * but only the registers up to this cap value are guaranteed to render
- * correctly.
- *
- * If guest-drivers are able to expose a lower-limit, it's recommended
- * that they clamp to this value. Otherwise, the host will make a
- * best-effort on case-by-case basis if guests exceed this.
- */
-#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
-
-/*
- * What is the maximum number of constant buffers that can be expected to
- * work correctly with a DX context?
- *
- * The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
- * anything in excess of this cap is not guaranteed to render correctly.
- *
- * If guest-drivers are able to expose a lower-limit, it's recommended
- * that they clamp to this value. Otherwise, the host will make a
- * best-effort on case-by-case basis if guests exceed this.
- */
-#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
-
-/*
- * Does the device support provoking vertex control?
- *
- * If this cap is present, the provokingVertexLast field in the
- * rasterizer state is enabled. (Guests can then set it to FALSE,
- * meaning that the first vertex is the provoking vertex, or TRUE,
- * meaning that the last verteix is the provoking vertex.)
- *
- * If this cap is FALSE, then guests should set the provokingVertexLast
- * to FALSE, otherwise rendering behavior is undefined.
- */
-#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
-
-#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
-#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
-#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
-#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
-#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
-#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
-#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
-#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
-#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
-#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
-#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
-#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
-#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
-#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
-#define SVGA3D_DEVCAP_DXFMT_DXT1 114
-#define SVGA3D_DEVCAP_DXFMT_DXT2 115
-#define SVGA3D_DEVCAP_DXFMT_DXT3 116
-#define SVGA3D_DEVCAP_DXFMT_DXT4 117
-#define SVGA3D_DEVCAP_DXFMT_DXT5 118
-#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
-#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
-#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
-#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
-#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
-#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
-#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
-#define SVGA3D_DEVCAP_DXFMT_V8U8 126
-#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
-#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
-#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
-#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
-#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
-#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
-#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
-#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
-#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
-#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
-#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
-#define SVGA3D_DEVCAP_DXFMT_V16U16 138
-#define SVGA3D_DEVCAP_DXFMT_G16R16 139
-#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
-#define SVGA3D_DEVCAP_DXFMT_UYVY 141
-#define SVGA3D_DEVCAP_DXFMT_YUY2 142
-#define SVGA3D_DEVCAP_DXFMT_NV12 143
-#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
-#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
-#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
-#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
-#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
-#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
-#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
-#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
-#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
-#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
-#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
-#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
-#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
-#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
-#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
-#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
-#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
-#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
-#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
-#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
-#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
-#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
-#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
-#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
-#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
-#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
-#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
-#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
-#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
-#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
-#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
-#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
-#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
-#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
-#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
-#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
-#define SVGA3D_DEVCAP_DXFMT_P8 196
-#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
-#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
-#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
-#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
-#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
-#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
-#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
-#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
-#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
-#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
-#define SVGA3D_DEVCAP_DXFMT_ATI1 207
-#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
-#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
-#define SVGA3D_DEVCAP_DXFMT_ATI2 210
-#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
-#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
-#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
-#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
-#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
-#define SVGA3D_DEVCAP_DXFMT_YV12 220
-#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
-#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
-#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
-#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
-#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
-#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
-#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
-#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
-#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
-#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
-#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
-#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
-#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
-#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
-#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
-#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
-#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
-#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
-#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
-#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
-#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
-
-/*
- * Advertises shaderModel 4.1 support, independent blend-states,
- * cube-map arrays, and a higher vertex input registers limit.
- *
- * (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
- */
-#define SVGA3D_DEVCAP_SM41 244
-#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
-#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
-
-/*
- * Indicates that the device has rendering support for
- * the full multisample quality. If this cap is not present,
- * the host may or may not support full quality rendering.
- *
- * See also SVGA_REG_MS_HINT_RESOLVED.
- */
-#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
-
-/*
- * Advertises support for the SVGA3D LogicOps commands.
- */
-#define SVGA3D_DEVCAP_LOGICOPS 248
-
-/*
- * Advertises support for using logicOps in the DXBlendStates.
- */
-#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
-
-/*
-* Note DXFMT range is now non-contiguous.
-*/
-#define SVGA3D_DEVCAP_RESERVED_1 250
-#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
-#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
-#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
-#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
-#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
-#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
-#define SVGA3D_DEVCAP_RESERVED_2 257
-
-#define SVGA3D_DEVCAP_SM5 258
-#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
-
-/* This must be the last index. */
-#define SVGA3D_DEVCAP_MAX 260
-
-/*
- * Bit definitions for DXFMT devcaps
- *
- *
- * SUPPORTED: Can the format be defined?
- * SHADER_SAMPLE: Can the format be sampled from a shader?
- * COLOR_RENDERTARGET: Can the format be a color render target?
- * DEPTH_RENDERTARGET: Can the format be a depth render target?
- * BLENDABLE: Is the format blendable?
- * MIPS: Does the format support mip levels?
- * ARRAY: Does the format support texture arrays?
- * VOLUME: Does the format support having volume?
- * MULTISAMPLE: Does the format support multisample?
- */
-#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
-#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
-#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
-#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
-#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
-#define SVGA3D_DXFMT_MIPS (1 << 5)
-#define SVGA3D_DXFMT_ARRAY (1 << 6)
-#define SVGA3D_DXFMT_VOLUME (1 << 7)
-#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
-#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
-#define SVGA3D_DXFMT_MAX (1 << 10)
+#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
+#define SVGA3D_DEVCAP_3D 0
+#define SVGA3D_DEVCAP_MAX_LIGHTS 1
+
+#define SVGA3D_DEVCAP_MAX_TEXTURES 2
+#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
+#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
+#define SVGA3D_DEVCAP_VERTEX_SHADER 5
+#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
+#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
+#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
+#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
+#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
+#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
+#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
+#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
+#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
+#define SVGA3D_DEVCAP_QUERY_TYPES 15
+#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
+#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
+#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
+#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
+#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
+#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
+#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
+#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
+#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
+#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
+#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
+#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
+#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
+#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
+#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
+#define SVGA3D_DEVCAP_TEXTURE_OPS 31
+#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
+#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
+#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
+#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
+#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
+#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
+#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
+#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
+#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
+#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
+#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
+#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
+#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
+#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
+#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
+#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
+#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
+#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
+#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
+#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
+#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
+#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
+#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
+#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
+#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
+#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
+#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
+
+#define SVGA3D_DEVCAP_MISSING62 62
+
+#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
+
+#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
+
+#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
+#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
+#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
+#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
+#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
+
+#define SVGA3D_DEVCAP_DEAD4 70
+#define SVGA3D_DEVCAP_DEAD5 71
+#define SVGA3D_DEVCAP_DEAD7 72
+#define SVGA3D_DEVCAP_DEAD6 73
+
+#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
+#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
+#define SVGA3D_DEVCAP_DEAD10 76
+
+#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
+
+#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
+
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
+#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
+
+#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
+#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
+
+#define SVGA3D_DEVCAP_DEAD1 84
+#define SVGA3D_DEVCAP_DEAD8 85
+#define SVGA3D_DEVCAP_DEAD9 86
+
+#define SVGA3D_DEVCAP_LINE_AA 87
+#define SVGA3D_DEVCAP_LINE_STIPPLE 88
+#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89
+#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90
+
+#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
+
+#define SVGA3D_DEVCAP_DEAD3 92
+
+#define SVGA3D_DEVCAP_TS_COLOR_KEY 93
+
+#define SVGA3D_DEVCAP_DEAD2 94
+
+#define SVGA3D_DEVCAP_DXCONTEXT 95
+
+#define SVGA3D_DEVCAP_DEAD11 96
+
+#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
+
+#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
+
+#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
+
+#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
+#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
+#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
+#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
+#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
+#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
+#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
+#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
+#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
+#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
+#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
+#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
+#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
+#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
+#define SVGA3D_DEVCAP_DXFMT_DXT1 114
+#define SVGA3D_DEVCAP_DXFMT_DXT2 115
+#define SVGA3D_DEVCAP_DXFMT_DXT3 116
+#define SVGA3D_DEVCAP_DXFMT_DXT4 117
+#define SVGA3D_DEVCAP_DXFMT_DXT5 118
+#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
+#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
+#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
+#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
+#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
+#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
+#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
+#define SVGA3D_DEVCAP_DXFMT_V8U8 126
+#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
+#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
+#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
+#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
+#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
+#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
+#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
+#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
+#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
+#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
+#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
+#define SVGA3D_DEVCAP_DXFMT_V16U16 138
+#define SVGA3D_DEVCAP_DXFMT_G16R16 139
+#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
+#define SVGA3D_DEVCAP_DXFMT_UYVY 141
+#define SVGA3D_DEVCAP_DXFMT_YUY2 142
+#define SVGA3D_DEVCAP_DXFMT_NV12 143
+#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
+#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
+#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
+#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
+#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
+#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
+#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
+#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
+#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
+#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
+#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
+#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
+#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
+#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
+#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
+#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
+#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
+#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
+#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
+#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
+#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
+#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
+#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
+#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
+#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
+#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
+#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
+#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
+#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
+#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
+#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
+#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
+#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
+#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
+#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
+#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
+#define SVGA3D_DEVCAP_DXFMT_P8 196
+#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
+#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
+#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
+#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
+#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
+#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
+#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
+#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
+#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
+#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
+#define SVGA3D_DEVCAP_DXFMT_ATI1 207
+#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
+#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
+#define SVGA3D_DEVCAP_DXFMT_ATI2 210
+#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
+#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
+#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
+#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
+#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
+#define SVGA3D_DEVCAP_DXFMT_YV12 220
+#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
+#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
+#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
+#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
+#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
+#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
+#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
+#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
+#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
+#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
+#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
+#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
+#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
+#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
+#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
+#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
+#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
+#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
+#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
+#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
+#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
+
+#define SVGA3D_DEVCAP_SM41 244
+#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
+#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
+
+#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
+
+#define SVGA3D_DEVCAP_LOGICOPS 248
+
+#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
+
+#define SVGA3D_DEVCAP_DEAD12 250
+
+#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
+#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
+#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
+#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
+#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
+#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
+
+#define SVGA3D_DEVCAP_DEAD13 257
+
+#define SVGA3D_DEVCAP_SM5 258
+#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
+
+#define SVGA3D_DEVCAP_MAX 262
+
+#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
+#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
+#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
+#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
+#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
+#define SVGA3D_DXFMT_MIPS (1 << 5)
+#define SVGA3D_DXFMT_ARRAY (1 << 6)
+#define SVGA3D_DXFMT_VOLUME (1 << 7)
+#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
+#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
+#define SVGA3D_DXFMT_MAX (1 << 10)
typedef union {
- SVGA3dBool b;
- uint32 u;
- int32 i;
- float f;
+ SVGA3dBool b;
+ uint32 u;
+ int32 i;
+ float f;
} SVGA3dDevCapResult;
-#endif /* _SVGA3D_DEVCAPS_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
index f703ac2b1768024e286f34cbdc1fc1fca397b961..5af442dad542d4b167f6f61b1db75616238a4621 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2012-2019 VMware, Inc.
+ * Copyright 2012-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,88 +27,70 @@
/*
* svga3d_dx.h --
*
- * SVGA 3d hardware definitions for DX10 support.
+ * SVGA 3d hardware definitions for DX10 support.
*/
+
+
#ifndef _SVGA3D_DX_H_
#define _SVGA3D_DX_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
-
+#include "svga_reg.h"
#include "svga3d_limits.h"
+#include "svga3d_types.h"
-#define SVGA3D_INPUT_MIN 0
-#define SVGA3D_INPUT_PER_VERTEX_DATA 0
+#define SVGA3D_INPUT_MIN 0
+#define SVGA3D_INPUT_PER_VERTEX_DATA 0
#define SVGA3D_INPUT_PER_INSTANCE_DATA 1
-#define SVGA3D_INPUT_MAX 2
+#define SVGA3D_INPUT_MAX 2
typedef uint32 SVGA3dInputClassification;
-#define SVGA3D_RESOURCE_TYPE_MIN 1
-#define SVGA3D_RESOURCE_BUFFER 1
-#define SVGA3D_RESOURCE_TEXTURE1D 2
-#define SVGA3D_RESOURCE_TEXTURE2D 3
-#define SVGA3D_RESOURCE_TEXTURE3D 4
-#define SVGA3D_RESOURCE_TEXTURECUBE 5
-#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
-#define SVGA3D_RESOURCE_BUFFEREX 6
-#define SVGA3D_RESOURCE_TYPE_MAX 7
-typedef uint32 SVGA3dResourceType;
-
-#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
-#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
-#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
-#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
-#define SVGA3D_COLOR_WRITE_ENABLE_ALL (SVGA3D_COLOR_WRITE_ENABLE_RED | \
- SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
- SVGA3D_COLOR_WRITE_ENABLE_BLUE | \
- SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
+#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
+#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
+#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
+#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
+#define SVGA3D_COLOR_WRITE_ENABLE_ALL \
+ (SVGA3D_COLOR_WRITE_ENABLE_RED | SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
+ SVGA3D_COLOR_WRITE_ENABLE_BLUE | SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
typedef uint8 SVGA3dColorWriteEnable;
-#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
-#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
+#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
+#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
typedef uint8 SVGA3dDepthWriteMask;
-#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
-#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
-#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
+#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
+#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
+#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
#define SVGA3D_FILTER_ANISOTROPIC (1 << 6)
-#define SVGA3D_FILTER_COMPARE (1 << 7)
+#define SVGA3D_FILTER_COMPARE (1 << 7)
typedef uint32 SVGA3dFilter;
#define SVGA3D_CULL_INVALID 0
-#define SVGA3D_CULL_MIN 1
-#define SVGA3D_CULL_NONE 1
-#define SVGA3D_CULL_FRONT 2
-#define SVGA3D_CULL_BACK 3
-#define SVGA3D_CULL_MAX 4
+#define SVGA3D_CULL_MIN 1
+#define SVGA3D_CULL_NONE 1
+#define SVGA3D_CULL_FRONT 2
+#define SVGA3D_CULL_BACK 3
+#define SVGA3D_CULL_MAX 4
typedef uint8 SVGA3dCullMode;
-#define SVGA3D_COMPARISON_INVALID 0
-#define SVGA3D_COMPARISON_MIN 1
-#define SVGA3D_COMPARISON_NEVER 1
-#define SVGA3D_COMPARISON_LESS 2
-#define SVGA3D_COMPARISON_EQUAL 3
-#define SVGA3D_COMPARISON_LESS_EQUAL 4
-#define SVGA3D_COMPARISON_GREATER 5
-#define SVGA3D_COMPARISON_NOT_EQUAL 6
-#define SVGA3D_COMPARISON_GREATER_EQUAL 7
-#define SVGA3D_COMPARISON_ALWAYS 8
-#define SVGA3D_COMPARISON_MAX 9
+#define SVGA3D_COMPARISON_INVALID 0
+#define SVGA3D_COMPARISON_MIN 1
+#define SVGA3D_COMPARISON_NEVER 1
+#define SVGA3D_COMPARISON_LESS 2
+#define SVGA3D_COMPARISON_EQUAL 3
+#define SVGA3D_COMPARISON_LESS_EQUAL 4
+#define SVGA3D_COMPARISON_GREATER 5
+#define SVGA3D_COMPARISON_NOT_EQUAL 6
+#define SVGA3D_COMPARISON_GREATER_EQUAL 7
+#define SVGA3D_COMPARISON_ALWAYS 8
+#define SVGA3D_COMPARISON_MAX 9
typedef uint8 SVGA3dComparisonFunc;
-/*
- * SVGA3D_MULTISAMPLE_RAST_DISABLE disables MSAA for all primitives.
- * SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE, which is supported in SM41,
- * disables MSAA for lines only.
- */
-#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
-#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
-#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
-#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
-#define SVGA3D_MULTISAMPLE_RAST_MAX 2
+#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
+#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
+#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
+#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
+#define SVGA3D_MULTISAMPLE_RAST_MAX 2
typedef uint8 SVGA3dMultisampleRastEnable;
#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
@@ -137,1531 +119,1273 @@ typedef uint32 SVGA3dQueryId;
typedef uint32 SVGA3dStreamOutputId;
typedef union {
- struct {
- float r;
- float g;
- float b;
- float a;
- };
-
- float value[4];
-} SVGA3dRGBAFloat;
-
-typedef union {
- struct {
- uint32 r;
- uint32 g;
- uint32 b;
- uint32 a;
- };
-
- uint32 value[4];
+ struct {
+ uint32 r;
+ uint32 g;
+ uint32 b;
+ uint32 a;
+ };
+
+ uint32 value[4];
} SVGA3dRGBAUint32;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 cid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGAOTableDXContextEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineContext; /* SVGA_3D_CMD_DX_DEFINE_CONTEXT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyContext; /* SVGA_3D_CMD_DX_DESTROY_CONTEXT */
-
-/*
- * Bind a DX context.
- *
- * validContents should be set to 0 for new contexts,
- * and 1 if this is an old context which is getting paged
- * back on to the device.
- *
- * For new contexts, it is recommended that the driver
- * issue commands to initialize all interesting state
- * prior to rendering.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindContext {
- uint32 cid;
- SVGAMobId mobid;
- uint32 validContents;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindContext; /* SVGA_3D_CMD_DX_BIND_CONTEXT */
-
-/*
- * Readback a DX context.
- * (Request that the device flush the contents back into guest memory.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXReadbackContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXReadbackContext; /* SVGA_3D_CMD_DX_READBACK_CONTEXT */
-
-/*
- * Invalidate a guest-backed context.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXInvalidateContext {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetSingleConstantBuffer {
- uint32 slot;
- SVGA3dShaderType type;
- SVGA3dSurfaceId sid;
- uint32 offsetInBytes;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetSingleConstantBuffer;
-/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetShaderResources {
- uint32 startView;
- SVGA3dShaderType type;
-
- /*
- * Followed by a variable number of SVGA3dShaderResourceViewId's.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetShaderResources; /* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetShader {
- SVGA3dShaderId shaderId;
- SVGA3dShaderType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetShader; /* SVGA_3D_CMD_DX_SET_SHADER */
+#pragma pack(push, 1)
+typedef struct {
+ uint32 cid;
+ SVGAMobId mobid;
+} SVGAOTableDXContextEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineContext {
+ uint32 cid;
+} SVGA3dCmdDXDefineContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyContext {
+ uint32 cid;
+} SVGA3dCmdDXDestroyContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindContext {
+ uint32 cid;
+ SVGAMobId mobid;
+ uint32 validContents;
+} SVGA3dCmdDXBindContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXReadbackContext {
+ uint32 cid;
+} SVGA3dCmdDXReadbackContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXInvalidateContext {
+ uint32 cid;
+} SVGA3dCmdDXInvalidateContext;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetSingleConstantBuffer {
+ uint32 slot;
+ SVGA3dShaderType type;
+ SVGA3dSurfaceId sid;
+ uint32 offsetInBytes;
+ uint32 sizeInBytes;
+} SVGA3dCmdDXSetSingleConstantBuffer;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetShaderResources {
+ uint32 startView;
+ SVGA3dShaderType type;
+
+} SVGA3dCmdDXSetShaderResources;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetShader {
+ SVGA3dShaderId shaderId;
+ SVGA3dShaderType type;
+} SVGA3dCmdDXSetShader;
+#pragma pack(pop)
typedef union {
- struct {
- uint32 cbOffset : 12;
- uint32 cbId : 4;
- uint32 baseSamp : 4;
- uint32 baseTex : 7;
- uint32 reserved : 5;
- };
- uint32 value;
+ struct {
+ uint32 cbOffset : 12;
+ uint32 cbId : 4;
+ uint32 baseSamp : 4;
+ uint32 baseTex : 7;
+ uint32 reserved : 5;
+ };
+ uint32 value;
} SVGA3dIfaceData;
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetShaderIface {
- SVGA3dShaderType type;
- uint32 numClassInstances;
- uint32 index;
- uint32 iface;
- SVGA3dIfaceData data;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetShaderIface; /* SVGA_3D_CMD_DX_SET_SHADER_IFACE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindShaderIface {
- uint32 cid;
- SVGAMobId mobid;
- uint32 offsetInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindShaderIface; /* SVGA_3D_CMD_DX_BIND_SHADER_IFACE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetSamplers {
- uint32 startSampler;
- SVGA3dShaderType type;
-
- /*
- * Followed by a variable number of SVGA3dSamplerId's.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetSamplers; /* SVGA_3D_CMD_DX_SET_SAMPLERS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDraw {
- uint32 vertexCount;
- uint32 startVertexLocation;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDraw; /* SVGA_3D_CMD_DX_DRAW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawIndexed {
- uint32 indexCount;
- uint32 startIndexLocation;
- int32 baseVertexLocation;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawIndexed; /* SVGA_3D_CMD_DX_DRAW_INDEXED */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawInstanced {
- uint32 vertexCountPerInstance;
- uint32 instanceCount;
- uint32 startVertexLocation;
- uint32 startInstanceLocation;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawInstanced; /* SVGA_3D_CMD_DX_DRAW_INSTANCED */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawIndexedInstanced {
- uint32 indexCountPerInstance;
- uint32 instanceCount;
- uint32 startIndexLocation;
- int32 baseVertexLocation;
- uint32 startInstanceLocation;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawIndexedInstanced; /* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawIndexedInstancedIndirect {
- SVGA3dSurfaceId argsBufferSid;
- uint32 byteOffsetForArgs;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawIndexedInstancedIndirect;
-/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawInstancedIndirect {
- SVGA3dSurfaceId argsBufferSid;
- uint32 byteOffsetForArgs;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawInstancedIndirect;
-/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDrawAuto {
- uint32 pad0;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDrawAuto; /* SVGA_3D_CMD_DX_DRAW_AUTO */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDispatch {
- uint32 threadGroupCountX;
- uint32 threadGroupCountY;
- uint32 threadGroupCountZ;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDispatch;
-/* SVGA_3D_CMD_DX_DISPATCH */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDispatchIndirect {
- SVGA3dSurfaceId argsBufferSid;
- uint32 byteOffsetForArgs;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDispatchIndirect;
-/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetInputLayout {
- SVGA3dElementLayoutId elementLayoutId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetInputLayout; /* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dVertexBuffer {
- SVGA3dSurfaceId sid;
- uint32 stride;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dVertexBuffer;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetVertexBuffers {
- uint32 startBuffer;
- /* Followed by a variable number of SVGA3dVertexBuffer's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetVertexBuffers; /* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetIndexBuffer {
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetIndexBuffer; /* SVGA_3D_CMD_DX_SET_INDEX_BUFFER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetTopology {
- SVGA3dPrimitiveType topology;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetTopology; /* SVGA_3D_CMD_DX_SET_TOPOLOGY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetRenderTargets {
- SVGA3dDepthStencilViewId depthStencilViewId;
- /* Followed by a variable number of SVGA3dRenderTargetViewId's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetRenderTargets; /* SVGA_3D_CMD_DX_SET_RENDERTARGETS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetBlendState {
- SVGA3dBlendStateId blendId;
- float blendFactor[4];
- uint32 sampleMask;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetBlendState; /* SVGA_3D_CMD_DX_SET_BLEND_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetDepthStencilState {
- SVGA3dDepthStencilStateId depthStencilId;
- uint32 stencilRef;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetDepthStencilState; /* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetRasterizerState {
- SVGA3dRasterizerStateId rasterizerId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetRasterizerState; /* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE */
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetShaderIface {
+ SVGA3dShaderType type;
+ uint32 numClassInstances;
+ uint32 index;
+ uint32 iface;
+ SVGA3dIfaceData data;
+} SVGA3dCmdDXSetShaderIface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindShaderIface {
+ uint32 cid;
+ SVGAMobId mobid;
+ uint32 offsetInBytes;
+} SVGA3dCmdDXBindShaderIface;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetSamplers {
+ uint32 startSampler;
+ SVGA3dShaderType type;
+
+} SVGA3dCmdDXSetSamplers;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDraw {
+ uint32 vertexCount;
+ uint32 startVertexLocation;
+} SVGA3dCmdDXDraw;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawIndexed {
+ uint32 indexCount;
+ uint32 startIndexLocation;
+ int32 baseVertexLocation;
+} SVGA3dCmdDXDrawIndexed;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawInstanced {
+ uint32 vertexCountPerInstance;
+ uint32 instanceCount;
+ uint32 startVertexLocation;
+ uint32 startInstanceLocation;
+} SVGA3dCmdDXDrawInstanced;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawIndexedInstanced {
+ uint32 indexCountPerInstance;
+ uint32 instanceCount;
+ uint32 startIndexLocation;
+ int32 baseVertexLocation;
+ uint32 startInstanceLocation;
+} SVGA3dCmdDXDrawIndexedInstanced;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawIndexedInstancedIndirect {
+ SVGA3dSurfaceId argsBufferSid;
+ uint32 byteOffsetForArgs;
+} SVGA3dCmdDXDrawIndexedInstancedIndirect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawInstancedIndirect {
+ SVGA3dSurfaceId argsBufferSid;
+ uint32 byteOffsetForArgs;
+} SVGA3dCmdDXDrawInstancedIndirect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDrawAuto {
+ uint32 pad0;
+} SVGA3dCmdDXDrawAuto;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDispatch {
+ uint32 threadGroupCountX;
+ uint32 threadGroupCountY;
+ uint32 threadGroupCountZ;
+} SVGA3dCmdDXDispatch;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDispatchIndirect {
+ SVGA3dSurfaceId argsBufferSid;
+ uint32 byteOffsetForArgs;
+} SVGA3dCmdDXDispatchIndirect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetInputLayout {
+ SVGA3dElementLayoutId elementLayoutId;
+} SVGA3dCmdDXSetInputLayout;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dVertexBuffer {
+ SVGA3dSurfaceId sid;
+ uint32 stride;
+ uint32 offset;
+} SVGA3dVertexBuffer;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetVertexBuffers {
+ uint32 startBuffer;
+
+} SVGA3dCmdDXSetVertexBuffers;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dVertexBuffer_v2 {
+ SVGA3dSurfaceId sid;
+ uint32 stride;
+ uint32 offset;
+ uint32 sizeInBytes;
+} SVGA3dVertexBuffer_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetVertexBuffers_v2 {
+ uint32 startBuffer;
+
+} SVGA3dCmdDXSetVertexBuffers_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dVertexBufferOffsetAndSize {
+ uint32 stride;
+ uint32 offset;
+ uint32 sizeInBytes;
+} SVGA3dVertexBufferOffsetAndSize;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetVertexBuffersOffsetAndSize {
+ uint32 startBuffer;
+
+} SVGA3dCmdDXSetVertexBuffersOffsetAndSize;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetIndexBuffer {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ uint32 offset;
+} SVGA3dCmdDXSetIndexBuffer;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetIndexBuffer_v2 {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ uint32 offset;
+ uint32 sizeInBytes;
+} SVGA3dCmdDXSetIndexBuffer_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetIndexBufferOffsetAndSize {
+ SVGA3dSurfaceFormat format;
+ uint32 offset;
+ uint32 sizeInBytes;
+} SVGA3dCmdDXSetIndexBufferOffsetAndSize;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetTopology {
+ SVGA3dPrimitiveType topology;
+} SVGA3dCmdDXSetTopology;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetRenderTargets {
+ SVGA3dDepthStencilViewId depthStencilViewId;
+
+} SVGA3dCmdDXSetRenderTargets;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetBlendState {
+ SVGA3dBlendStateId blendId;
+ float blendFactor[4];
+ uint32 sampleMask;
+} SVGA3dCmdDXSetBlendState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetDepthStencilState {
+ SVGA3dDepthStencilStateId depthStencilId;
+ uint32 stencilRef;
+} SVGA3dCmdDXSetDepthStencilState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetRasterizerState {
+ SVGA3dRasterizerStateId rasterizerId;
+} SVGA3dCmdDXSetRasterizerState;
+#pragma pack(pop)
#define SVGA3D_DXQUERY_FLAG_PREDICATEHINT (1 << 0)
typedef uint32 SVGA3dDXQueryFlags;
-/*
- * The SVGADXQueryDeviceState and SVGADXQueryDeviceBits are used by the device
- * to track query state transitions, but are not intended to be used by the
- * driver.
- */
-#define SVGADX_QDSTATE_INVALID ((uint8)-1) /* Query has no state */
-#define SVGADX_QDSTATE_MIN 0
-#define SVGADX_QDSTATE_IDLE 0 /* Query hasn't started yet */
-#define SVGADX_QDSTATE_ACTIVE 1 /* Query is actively gathering data */
-#define SVGADX_QDSTATE_PENDING 2 /* Query is waiting for results */
-#define SVGADX_QDSTATE_FINISHED 3 /* Query has completed */
-#define SVGADX_QDSTATE_MAX 4
+#define SVGADX_QDSTATE_INVALID ((uint8)-1)
+#define SVGADX_QDSTATE_MIN 0
+#define SVGADX_QDSTATE_IDLE 0
+#define SVGADX_QDSTATE_ACTIVE 1
+#define SVGADX_QDSTATE_PENDING 2
+#define SVGADX_QDSTATE_FINISHED 3
+#define SVGADX_QDSTATE_MAX 4
typedef uint8 SVGADXQueryDeviceState;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dQueryTypeUint8 type;
- uint16 pad0;
- SVGADXQueryDeviceState state;
- SVGA3dDXQueryFlags flags;
- SVGAMobId mobid;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXQueryEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineQuery {
- SVGA3dQueryId queryId;
- SVGA3dQueryType type;
- SVGA3dDXQueryFlags flags;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineQuery; /* SVGA_3D_CMD_DX_DEFINE_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyQuery {
- SVGA3dQueryId queryId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyQuery; /* SVGA_3D_CMD_DX_DESTROY_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindQuery {
- SVGA3dQueryId queryId;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindQuery; /* SVGA_3D_CMD_DX_BIND_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetQueryOffset {
- SVGA3dQueryId queryId;
- uint32 mobOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetQueryOffset; /* SVGA_3D_CMD_DX_SET_QUERY_OFFSET */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBeginQuery {
- SVGA3dQueryId queryId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBeginQuery; /* SVGA_3D_CMD_DX_QUERY_BEGIN */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXEndQuery {
- SVGA3dQueryId queryId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXEndQuery; /* SVGA_3D_CMD_DX_QUERY_END */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXReadbackQuery {
- SVGA3dQueryId queryId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXReadbackQuery; /* SVGA_3D_CMD_DX_READBACK_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXMoveQuery {
- SVGA3dQueryId queryId;
- SVGAMobId mobid;
- uint32 mobOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXMoveQuery; /* SVGA_3D_CMD_DX_MOVE_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindAllQuery {
- uint32 cid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindAllQuery; /* SVGA_3D_CMD_DX_BIND_ALL_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXReadbackAllQuery {
- uint32 cid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXReadbackAllQuery; /* SVGA_3D_CMD_DX_READBACK_ALL_QUERY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetPredication {
- SVGA3dQueryId queryId;
- uint32 predicateValue;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetPredication; /* SVGA_3D_CMD_DX_SET_PREDICATION */
-
-typedef
-#include "vmware_pack_begin.h"
-struct MKS3dDXSOState {
- uint32 offset; /* Starting offset */
- uint32 intOffset; /* Internal offset */
- uint32 vertexCount; /* vertices written */
- uint32 dead;
-}
-#include "vmware_pack_end.h"
-SVGA3dDXSOState;
-
-/* Set the offset field to this value to append SO values to the buffer */
-#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32) ~0u)
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dSoTarget {
- SVGA3dSurfaceId sid;
- uint32 offset;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dSoTarget;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetSOTargets {
- uint32 pad0;
- /* Followed by a variable number of SVGA3dSOTarget's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetSOTargets; /* SVGA_3D_CMD_DX_SET_SOTARGETS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dViewport
-{
- float x;
- float y;
- float width;
- float height;
- float minDepth;
- float maxDepth;
-}
-#include "vmware_pack_end.h"
-SVGA3dViewport;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetViewports {
- uint32 pad0;
- /* Followed by a variable number of SVGA3dViewport's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetViewports; /* SVGA_3D_CMD_DX_SET_VIEWPORTS */
-
-#define SVGA3D_DX_MAX_VIEWPORTS 16
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetScissorRects {
- uint32 pad0;
- /* Followed by a variable number of SVGASignedRect's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetScissorRects; /* SVGA_3D_CMD_DX_SET_SCISSORRECTS */
-
-#define SVGA3D_DX_MAX_SCISSORRECTS 16
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXClearRenderTargetView {
- SVGA3dRenderTargetViewId renderTargetViewId;
- SVGA3dRGBAFloat rgba;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXClearRenderTargetView; /* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXClearDepthStencilView {
- uint16 flags;
- uint16 stencil;
- SVGA3dDepthStencilViewId depthStencilViewId;
- float depth;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXClearDepthStencilView; /* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPredCopyRegion {
- SVGA3dSurfaceId dstSid;
- uint32 dstSubResource;
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dCopyBox box;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredCopyRegion;
-/* SVGA_3D_CMD_DX_PRED_COPY_REGION */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPredCopy {
- SVGA3dSurfaceId dstSid;
- SVGA3dSurfaceId srcSid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPredConvertRegion {
- SVGA3dSurfaceId dstSid;
- uint32 dstSubResource;
- SVGA3dBox destBox;
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dBox srcBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredConvertRegion; /* SVGA_3D_CMD_DX_PRED_CONVERT_REGION */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPredConvert {
- SVGA3dSurfaceId dstSid;
- SVGA3dSurfaceId srcSid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredConvert; /* SVGA_3D_CMD_DX_PRED_CONVERT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBufferCopy {
- SVGA3dSurfaceId dest;
- SVGA3dSurfaceId src;
- uint32 destX;
- uint32 srcX;
- uint32 width;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBufferCopy;
-/* SVGA_3D_CMD_DX_BUFFER_COPY */
-
-/*
- * Perform a surface copy between a multisample, and a non-multisampled
- * surface.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId dstSid;
- uint32 dstSubResource;
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dSurfaceFormat copyFormat;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXResolveCopy; /* SVGA_3D_CMD_DX_RESOLVE_COPY */
-
-/*
- * Perform a predicated surface copy between a multisample, and a
- * non-multisampled surface.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId dstSid;
- uint32 dstSubResource;
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dSurfaceFormat copyFormat;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredResolveCopy; /* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY */
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dQueryTypeUint8 type;
+ uint16 pad0;
+ SVGADXQueryDeviceState state;
+ SVGA3dDXQueryFlags flags;
+ SVGAMobId mobid;
+ uint32 offset;
+} SVGACOTableDXQueryEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineQuery {
+ SVGA3dQueryId queryId;
+ SVGA3dQueryType type;
+ SVGA3dDXQueryFlags flags;
+} SVGA3dCmdDXDefineQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyQuery {
+ SVGA3dQueryId queryId;
+} SVGA3dCmdDXDestroyQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindQuery {
+ SVGA3dQueryId queryId;
+ SVGAMobId mobid;
+} SVGA3dCmdDXBindQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetQueryOffset {
+ SVGA3dQueryId queryId;
+ uint32 mobOffset;
+} SVGA3dCmdDXSetQueryOffset;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBeginQuery {
+ SVGA3dQueryId queryId;
+} SVGA3dCmdDXBeginQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXEndQuery {
+ SVGA3dQueryId queryId;
+} SVGA3dCmdDXEndQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXReadbackQuery {
+ SVGA3dQueryId queryId;
+} SVGA3dCmdDXReadbackQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXMoveQuery {
+ SVGA3dQueryId queryId;
+ SVGAMobId mobid;
+ uint32 mobOffset;
+} SVGA3dCmdDXMoveQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindAllQuery {
+ uint32 cid;
+ SVGAMobId mobid;
+} SVGA3dCmdDXBindAllQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXReadbackAllQuery {
+ uint32 cid;
+} SVGA3dCmdDXReadbackAllQuery;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetPredication {
+ SVGA3dQueryId queryId;
+ uint32 predicateValue;
+} SVGA3dCmdDXSetPredication;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct MKS3dDXSOState {
+ uint32 offset;
+ uint32 intOffset;
+ uint32 vertexCount;
+ uint32 dead;
+} SVGA3dDXSOState;
+#pragma pack(pop)
+
+#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32)~0u)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dSoTarget {
+ SVGA3dSurfaceId sid;
+ uint32 offset;
+ uint32 sizeInBytes;
+} SVGA3dSoTarget;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetSOTargets {
+ uint32 pad0;
+
+} SVGA3dCmdDXSetSOTargets;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dViewport {
+ float x;
+ float y;
+ float width;
+ float height;
+ float minDepth;
+ float maxDepth;
+} SVGA3dViewport;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetViewports {
+ uint32 pad0;
+
+} SVGA3dCmdDXSetViewports;
+#pragma pack(pop)
+
+#define SVGA3D_DX_MAX_VIEWPORTS 16
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetScissorRects {
+ uint32 pad0;
+
+} SVGA3dCmdDXSetScissorRects;
+#pragma pack(pop)
+
+#define SVGA3D_DX_MAX_SCISSORRECTS 16
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXClearRenderTargetView {
+ SVGA3dRenderTargetViewId renderTargetViewId;
+ SVGA3dRGBAFloat rgba;
+} SVGA3dCmdDXClearRenderTargetView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXClearDepthStencilView {
+ uint16 flags;
+ uint16 stencil;
+ SVGA3dDepthStencilViewId depthStencilViewId;
+ float depth;
+} SVGA3dCmdDXClearDepthStencilView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredCopyRegion {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dCopyBox box;
+} SVGA3dCmdDXPredCopyRegion;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredStagingCopyRegion {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dCopyBox box;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+} SVGA3dCmdDXPredStagingCopyRegion;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredCopy {
+ SVGA3dSurfaceId dstSid;
+ SVGA3dSurfaceId srcSid;
+} SVGA3dCmdDXPredCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredConvertRegion {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dBox destBox;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dBox srcBox;
+} SVGA3dCmdDXPredConvertRegion;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredStagingConvertRegion {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dBox destBox;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dBox srcBox;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+} SVGA3dCmdDXPredStagingConvertRegion;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredConvert {
+ SVGA3dSurfaceId dstSid;
+ SVGA3dSurfaceId srcSid;
+} SVGA3dCmdDXPredConvert;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredStagingConvert {
+ SVGA3dSurfaceId dstSid;
+ SVGA3dSurfaceId srcSid;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+} SVGA3dCmdDXPredStagingConvert;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBufferCopy {
+ SVGA3dSurfaceId dest;
+ SVGA3dSurfaceId src;
+ uint32 destX;
+ uint32 srcX;
+ uint32 width;
+} SVGA3dCmdDXBufferCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXStagingBufferCopy {
+ SVGA3dSurfaceId dest;
+ SVGA3dSurfaceId src;
+ uint32 destX;
+ uint32 srcX;
+ uint32 width;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+} SVGA3dCmdDXStagingBufferCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dSurfaceFormat copyFormat;
+} SVGA3dCmdDXResolveCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId dstSid;
+ uint32 dstSubResource;
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dSurfaceFormat copyFormat;
+} SVGA3dCmdDXPredResolveCopy;
+#pragma pack(pop)
typedef uint32 SVGA3dDXPresentBltMode;
-#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
-#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
+#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
+#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
#define SVGADX_PRESENTBLT_FORCE_SRC_XRBIAS (1 << 2)
-#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPresentBlt {
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dSurfaceId dstSid;
- uint32 destSubResource;
- SVGA3dBox boxSrc;
- SVGA3dBox boxDest;
- SVGA3dDXPresentBltMode mode;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPresentBlt; /* SVGA_3D_CMD_DX_PRESENTBLT*/
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXGenMips {
- SVGA3dShaderResourceViewId shaderResourceViewId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
-
-/*
- * Update a sub-resource in a guest-backed resource.
- * (Inform the device that the guest-contents have been updated.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXUpdateSubResource {
- SVGA3dSurfaceId sid;
- uint32 subResource;
- SVGA3dBox box;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXUpdateSubResource; /* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE */
-
-/*
- * Readback a subresource in a guest-backed resource.
- * (Request the device to flush the dirty contents into the guest.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXReadbackSubResource {
- SVGA3dSurfaceId sid;
- uint32 subResource;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXReadbackSubResource; /* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE */
-
-/*
- * Invalidate an image in a guest-backed surface.
- * (Notify the device that the contents can be lost.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXInvalidateSubResource {
- SVGA3dSurfaceId sid;
- uint32 subResource;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
-
-
-/*
- * Raw byte wise transfer from a buffer surface into another surface
- * of the requested box. Supported if 3d is enabled and SVGA_CAP_DX
- * is set. This command does not take a context.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXTransferFromBuffer {
- SVGA3dSurfaceId srcSid;
- uint32 srcOffset;
- uint32 srcPitch;
- uint32 srcSlicePitch;
- SVGA3dSurfaceId destSid;
- uint32 destSubResource;
- SVGA3dBox destBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXTransferFromBuffer; /* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER */
-
-
-#define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0)
+#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPresentBlt {
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dSurfaceId dstSid;
+ uint32 destSubResource;
+ SVGA3dBox boxSrc;
+ SVGA3dBox boxDest;
+ SVGA3dDXPresentBltMode mode;
+} SVGA3dCmdDXPresentBlt;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXGenMips {
+ SVGA3dShaderResourceViewId shaderResourceViewId;
+} SVGA3dCmdDXGenMips;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXUpdateSubResource {
+ SVGA3dSurfaceId sid;
+ uint32 subResource;
+ SVGA3dBox box;
+} SVGA3dCmdDXUpdateSubResource;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXReadbackSubResource {
+ SVGA3dSurfaceId sid;
+ uint32 subResource;
+} SVGA3dCmdDXReadbackSubResource;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXInvalidateSubResource {
+ SVGA3dSurfaceId sid;
+ uint32 subResource;
+} SVGA3dCmdDXInvalidateSubResource;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXTransferFromBuffer {
+ SVGA3dSurfaceId srcSid;
+ uint32 srcOffset;
+ uint32 srcPitch;
+ uint32 srcSlicePitch;
+ SVGA3dSurfaceId destSid;
+ uint32 destSubResource;
+ SVGA3dBox destBox;
+} SVGA3dCmdDXTransferFromBuffer;
+#pragma pack(pop)
+
+#define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0)
#define SVGA3D_TRANSFER_TO_BUFFER_FLAGS_MASK (1 << 0)
typedef uint32 SVGA3dTransferToBufferFlags;
-/*
- * Raw byte wise transfer to a buffer surface from another surface
- * of the requested box. Supported if SVGA_CAP_DX2 is set. This
- * command does not take a context.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXTransferToBuffer {
- SVGA3dSurfaceId srcSid;
- uint32 srcSubResource;
- SVGA3dBox srcBox;
- SVGA3dSurfaceId destSid;
- uint32 destOffset;
- uint32 destPitch;
- uint32 destSlicePitch;
- SVGA3dTransferToBufferFlags flags;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXTransferToBuffer; /* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER */
-
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXTransferToBuffer {
+ SVGA3dSurfaceId srcSid;
+ uint32 srcSubResource;
+ SVGA3dBox srcBox;
+ SVGA3dSurfaceId destSid;
+ uint32 destOffset;
+ uint32 destPitch;
+ uint32 destSlicePitch;
+ SVGA3dTransferToBufferFlags flags;
+} SVGA3dCmdDXTransferToBuffer;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredTransferFromBuffer {
+ SVGA3dSurfaceId srcSid;
+ uint32 srcOffset;
+ uint32 srcPitch;
+ uint32 srcSlicePitch;
+ SVGA3dSurfaceId destSid;
+ uint32 destSubResource;
+ SVGA3dBox destBox;
+} SVGA3dCmdDXPredTransferFromBuffer;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSurfaceCopyAndReadback {
+ SVGA3dSurfaceId srcSid;
+ SVGA3dSurfaceId destSid;
+ SVGA3dCopyBox box;
+} SVGA3dCmdDXSurfaceCopyAndReadback;
+#pragma pack(pop)
-/*
- * Raw byte wise transfer from a buffer surface into another surface
- * of the requested box. Supported if SVGA3D_DEVCAP_DXCONTEXT is set.
- * The context is implied from the command buffer header.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXPredTransferFromBuffer {
- SVGA3dSurfaceId srcSid;
- uint32 srcOffset;
- uint32 srcPitch;
- uint32 srcSlicePitch;
- SVGA3dSurfaceId destSid;
- uint32 destSubResource;
- SVGA3dBox destBox;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXPredTransferFromBuffer;
-/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER */
-
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSurfaceCopyAndReadback {
- SVGA3dSurfaceId srcSid;
- SVGA3dSurfaceId destSid;
- SVGA3dCopyBox box;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSurfaceCopyAndReadback;
-/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
-
-/*
- * SVGA_DX_HINT_NONE: Does nothing.
- *
- * SVGA_DX_HINT_PREFETCH_OBJECT:
- * SVGA_DX_HINT_PREEVICT_OBJECT:
- * Consumes a SVGAObjectRef, and hints that the host should consider
- * fetching/evicting the specified object.
- *
- * An id of SVGA3D_INVALID_ID can be used if the guest isn't sure
- * what object was affected. (For instance, if the guest knows that
- * it is about to evict a DXShader, but doesn't know precisely which one,
- * the device can still use this to help limit it's search, or track
- * how many page-outs have happened.)
- *
- * SVGA_DX_HINT_PREFETCH_COBJECT:
- * SVGA_DX_HINT_PREEVICT_COBJECT:
- * Same as the above, except they consume an SVGACObjectRef.
- */
typedef uint32 SVGADXHintId;
-#define SVGA_DX_HINT_NONE 0
-#define SVGA_DX_HINT_PREFETCH_OBJECT 1
-#define SVGA_DX_HINT_PREEVICT_OBJECT 2
-#define SVGA_DX_HINT_PREFETCH_COBJECT 3
-#define SVGA_DX_HINT_PREEVICT_COBJECT 4
-#define SVGA_DX_HINT_MAX 5
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAObjectRef {
- SVGAOTableType type;
- uint32 id;
-}
-#include "vmware_pack_end.h"
-SVGAObjectRef;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGACObjectRef {
- SVGACOTableType type;
- uint32 cid;
- uint32 id;
-}
-#include "vmware_pack_end.h"
-SVGACObjectRef;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXHint {
- SVGADXHintId hintId;
-
- /*
- * Followed by variable sized data depending on the hintId.
- */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXHint;
-/* SVGA_3D_CMD_DX_HINT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBufferUpdate {
- SVGA3dSurfaceId sid;
- uint32 x;
- uint32 width;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBufferUpdate;
-/* SVGA_3D_CMD_DX_BUFFER_UPDATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetConstantBufferOffset {
- uint32 slot;
- uint32 offsetInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetConstantBufferOffset;
+#define SVGA_DX_HINT_NONE 0
+#define SVGA_DX_HINT_PREFETCH_OBJECT 1
+#define SVGA_DX_HINT_PREEVICT_OBJECT 2
+#define SVGA_DX_HINT_PREFETCH_COBJECT 3
+#define SVGA_DX_HINT_PREEVICT_COBJECT 4
+#define SVGA_DX_HINT_MAX 5
+
+#pragma pack(push, 1)
+typedef struct SVGAObjectRef {
+ SVGAOTableType type;
+ uint32 id;
+} SVGAObjectRef;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGACObjectRef {
+ SVGACOTableType type;
+ uint32 cid;
+ uint32 id;
+} SVGACObjectRef;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXHint {
+ SVGADXHintId hintId;
+
+} SVGA3dCmdDXHint;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBufferUpdate {
+ SVGA3dSurfaceId sid;
+ uint32 x;
+ uint32 width;
+} SVGA3dCmdDXBufferUpdate;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetConstantBufferOffset {
+ uint32 slot;
+ uint32 offsetInBytes;
+} SVGA3dCmdDXSetConstantBufferOffset;
+#pragma pack(pop)
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetVSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetHSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetDSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET */
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetCSConstantBufferOffset;
-/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET */
-
-#define SVGA3D_BUFFEREX_SRV_RAW (1 << 0)
-#define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1)
+#define SVGA3D_BUFFEREX_SRV_RAW (1 << 0)
+#define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1)
#define SVGA3D_BUFFEREX_SRV_FLAGS_MASK (SVGA3D_BUFFEREX_SRV_FLAGS_MAX - 1)
typedef uint32 SVGA3dBufferExFlags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- union {
- struct {
- uint32 firstElement;
- uint32 numElements;
- uint32 pad0;
- uint32 pad1;
- } buffer;
- struct {
- uint32 mostDetailedMip;
- uint32 firstArraySlice;
- uint32 mipLevels;
- uint32 arraySize;
- } tex; /* 1d, 2d, 3d, cube */
- struct {
- uint32 firstElement;
- uint32 numElements;
- SVGA3dBufferExFlags flags;
- uint32 pad0;
- } bufferex;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dShaderResourceViewDesc;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- SVGA3dShaderResourceViewDesc desc;
- uint32 pad;
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXSRViewEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineShaderResourceView {
- SVGA3dShaderResourceViewId shaderResourceViewId;
-
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
-
- SVGA3dShaderResourceViewDesc desc;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineShaderResourceView;
-/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyShaderResourceView {
- SVGA3dShaderResourceViewId shaderResourceViewId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyShaderResourceView;
-/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dRenderTargetViewDesc {
- union {
- struct {
- uint32 firstElement;
- uint32 numElements;
- uint32 padding0;
- } buffer;
- struct {
- uint32 mipSlice;
- uint32 firstArraySlice;
- uint32 arraySize;
- } tex; /* 1d, 2d, cube */
- struct {
- uint32 mipSlice;
- uint32 firstW;
- uint32 wSize;
- } tex3D;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dRenderTargetViewDesc;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- SVGA3dRenderTargetViewDesc desc;
- uint32 pad[2];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXRTViewEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineRenderTargetView {
- SVGA3dRenderTargetViewId renderTargetViewId;
-
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
-
- SVGA3dRenderTargetViewDesc desc;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineRenderTargetView;
-/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyRenderTargetView {
- SVGA3dRenderTargetViewId renderTargetViewId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyRenderTargetView;
-/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW */
-
-/*
- */
-#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
+#pragma pack(push, 1)
+typedef struct {
+ union {
+ struct {
+ uint32 firstElement;
+ uint32 numElements;
+ uint32 pad0;
+ uint32 pad1;
+ } buffer;
+ struct {
+ uint32 mostDetailedMip;
+ uint32 firstArraySlice;
+ uint32 mipLevels;
+ uint32 arraySize;
+ } tex;
+ struct {
+ uint32 firstElement;
+ uint32 numElements;
+ SVGA3dBufferExFlags flags;
+ uint32 pad0;
+ } bufferex;
+ };
+} SVGA3dShaderResourceViewDesc;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ SVGA3dShaderResourceViewDesc desc;
+ uint32 pad;
+} SVGACOTableDXSRViewEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineShaderResourceView {
+ SVGA3dShaderResourceViewId shaderResourceViewId;
+
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+
+ SVGA3dShaderResourceViewDesc desc;
+} SVGA3dCmdDXDefineShaderResourceView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyShaderResourceView {
+ SVGA3dShaderResourceViewId shaderResourceViewId;
+} SVGA3dCmdDXDestroyShaderResourceView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dRenderTargetViewDesc {
+ union {
+ struct {
+ uint32 firstElement;
+ uint32 numElements;
+ uint32 padding0;
+ } buffer;
+ struct {
+ uint32 mipSlice;
+ uint32 firstArraySlice;
+ uint32 arraySize;
+ } tex;
+ struct {
+ uint32 mipSlice;
+ uint32 firstW;
+ uint32 wSize;
+ } tex3D;
+ };
+} SVGA3dRenderTargetViewDesc;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ SVGA3dRenderTargetViewDesc desc;
+ uint32 pad[2];
+} SVGACOTableDXRTViewEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineRenderTargetView {
+ SVGA3dRenderTargetViewId renderTargetViewId;
+
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+
+ SVGA3dRenderTargetViewDesc desc;
+} SVGA3dCmdDXDefineRenderTargetView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyRenderTargetView {
+ SVGA3dRenderTargetViewId renderTargetViewId;
+} SVGA3dCmdDXDestroyRenderTargetView;
+#pragma pack(pop)
+
+#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_STENCIL 0x02
-#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
+#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
typedef uint8 SVGA3DCreateDSViewFlags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- uint32 mipSlice;
- uint32 firstArraySlice;
- uint32 arraySize;
- SVGA3DCreateDSViewFlags flags;
- uint8 pad0;
- uint16 pad1;
- uint32 pad2;
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXDSViewEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineDepthStencilView {
- SVGA3dDepthStencilViewId depthStencilViewId;
-
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- uint32 mipSlice;
- uint32 firstArraySlice;
- uint32 arraySize;
- SVGA3DCreateDSViewFlags flags;
- uint8 pad0;
- uint16 pad1;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineDepthStencilView;
-/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW */
-
-/*
- * Version 2 needed in order to start validating and using the flags
- * field. Unfortunately the device wasn't validating or using the
- * flags field and the driver wasn't initializing it in shipped code,
- * so a new version of the command is needed to allow that code to
- * continue to work.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineDepthStencilView_v2 {
- SVGA3dDepthStencilViewId depthStencilViewId;
-
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- uint32 mipSlice;
- uint32 firstArraySlice;
- uint32 arraySize;
- SVGA3DCreateDSViewFlags flags;
- uint8 pad0;
- uint16 pad1;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineDepthStencilView_v2;
-/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyDepthStencilView {
- SVGA3dDepthStencilViewId depthStencilViewId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyDepthStencilView;
-/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW */
-
-
-#define SVGA3D_UABUFFER_RAW (1 << 0)
-#define SVGA3D_UABUFFER_APPEND (1 << 1)
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ uint32 mipSlice;
+ uint32 firstArraySlice;
+ uint32 arraySize;
+ SVGA3DCreateDSViewFlags flags;
+ uint8 pad0;
+ uint16 pad1;
+ uint32 pad2;
+} SVGACOTableDXDSViewEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineDepthStencilView {
+ SVGA3dDepthStencilViewId depthStencilViewId;
+
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ uint32 mipSlice;
+ uint32 firstArraySlice;
+ uint32 arraySize;
+ SVGA3DCreateDSViewFlags flags;
+ uint8 pad0;
+ uint16 pad1;
+} SVGA3dCmdDXDefineDepthStencilView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineDepthStencilView_v2 {
+ SVGA3dDepthStencilViewId depthStencilViewId;
+
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ uint32 mipSlice;
+ uint32 firstArraySlice;
+ uint32 arraySize;
+ SVGA3DCreateDSViewFlags flags;
+ uint8 pad0;
+ uint16 pad1;
+} SVGA3dCmdDXDefineDepthStencilView_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyDepthStencilView {
+ SVGA3dDepthStencilViewId depthStencilViewId;
+} SVGA3dCmdDXDestroyDepthStencilView;
+#pragma pack(pop)
+
+#define SVGA3D_UABUFFER_RAW (1 << 0)
+#define SVGA3D_UABUFFER_APPEND (1 << 1)
#define SVGA3D_UABUFFER_COUNTER (1 << 2)
typedef uint32 SVGA3dUABufferFlags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- union {
- struct {
- uint32 firstElement;
- uint32 numElements;
- SVGA3dUABufferFlags flags;
- uint32 padding0;
- uint32 padding1;
- } buffer;
- struct {
- uint32 mipSlice;
- uint32 firstArraySlice;
- uint32 arraySize;
- uint32 padding0;
- uint32 padding1;
- } tex; /* 1d, 2d */
- struct {
- uint32 mipSlice;
- uint32 firstW;
- uint32 wSize;
- uint32 padding0;
- uint32 padding1;
- } tex3D;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dUAViewDesc;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
- SVGA3dUAViewDesc desc;
- uint32 structureCount;
- uint32 pad[7];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXUAViewEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineUAView {
- SVGA3dUAViewId uaViewId;
-
- SVGA3dSurfaceId sid;
- SVGA3dSurfaceFormat format;
- SVGA3dResourceType resourceDimension;
-
- SVGA3dUAViewDesc desc;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineUAView;
-/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyUAView {
- SVGA3dUAViewId uaViewId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyUAView;
-/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXClearUAViewUint {
- SVGA3dUAViewId uaViewId;
- SVGA3dRGBAUint32 value;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXClearUAViewUint;
-/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXClearUAViewFloat {
- SVGA3dUAViewId uaViewId;
- SVGA3dRGBAFloat value;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXClearUAViewFloat;
-/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXCopyStructureCount {
- SVGA3dUAViewId srcUAViewId;
- SVGA3dSurfaceId destSid;
- uint32 destByteOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXCopyStructureCount;
-/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetStructureCount {
- SVGA3dUAViewId uaViewId;
- uint32 structureCount;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetStructureCount;
-/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetUAViews {
- uint32 uavSpliceIndex;
- /* Followed by a variable number of SVGA3dUAViewId's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetUAViews; /* SVGA_3D_CMD_DX_SET_UA_VIEWS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetCSUAViews {
- uint32 startIndex;
- /* Followed by a variable number of SVGA3dUAViewId's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetCSUAViews; /* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dInputElementDesc {
- uint32 inputSlot;
- uint32 alignedByteOffset;
- SVGA3dSurfaceFormat format;
- SVGA3dInputClassification inputSlotClass;
- uint32 instanceDataStepRate;
- uint32 inputRegister;
-}
-#include "vmware_pack_end.h"
-SVGA3dInputElementDesc;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 elid;
- uint32 numDescs;
- SVGA3dInputElementDesc descs[32];
- uint32 pad[62];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXElementLayoutEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineElementLayout {
- SVGA3dElementLayoutId elementLayoutId;
- /* Followed by a variable number of SVGA3dInputElementDesc's. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineElementLayout;
-/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyElementLayout {
- SVGA3dElementLayoutId elementLayoutId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyElementLayout;
-/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT */
-
+#pragma pack(push, 1)
+typedef struct {
+ union {
+ struct {
+ uint32 firstElement;
+ uint32 numElements;
+ SVGA3dUABufferFlags flags;
+ uint32 padding0;
+ uint32 padding1;
+ } buffer;
+ struct {
+ uint32 mipSlice;
+ uint32 firstArraySlice;
+ uint32 arraySize;
+ uint32 padding0;
+ uint32 padding1;
+ } tex;
+ struct {
+ uint32 mipSlice;
+ uint32 firstW;
+ uint32 wSize;
+ uint32 padding0;
+ uint32 padding1;
+ } tex3D;
+ };
+} SVGA3dUAViewDesc;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+ SVGA3dUAViewDesc desc;
+ uint32 structureCount;
+ uint32 pad[7];
+} SVGACOTableDXUAViewEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineUAView {
+ SVGA3dUAViewId uaViewId;
+
+ SVGA3dSurfaceId sid;
+ SVGA3dSurfaceFormat format;
+ SVGA3dResourceType resourceDimension;
+
+ SVGA3dUAViewDesc desc;
+} SVGA3dCmdDXDefineUAView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyUAView {
+ SVGA3dUAViewId uaViewId;
+} SVGA3dCmdDXDestroyUAView;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXClearUAViewUint {
+ SVGA3dUAViewId uaViewId;
+ SVGA3dRGBAUint32 value;
+} SVGA3dCmdDXClearUAViewUint;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXClearUAViewFloat {
+ SVGA3dUAViewId uaViewId;
+ SVGA3dRGBAFloat value;
+} SVGA3dCmdDXClearUAViewFloat;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXCopyStructureCount {
+ SVGA3dUAViewId srcUAViewId;
+ SVGA3dSurfaceId destSid;
+ uint32 destByteOffset;
+} SVGA3dCmdDXCopyStructureCount;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetStructureCount {
+ SVGA3dUAViewId uaViewId;
+ uint32 structureCount;
+} SVGA3dCmdDXSetStructureCount;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetUAViews {
+ uint32 uavSpliceIndex;
+
+} SVGA3dCmdDXSetUAViews;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetCSUAViews {
+ uint32 startIndex;
+
+} SVGA3dCmdDXSetCSUAViews;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dInputElementDesc {
+ uint32 inputSlot;
+ uint32 alignedByteOffset;
+ SVGA3dSurfaceFormat format;
+ SVGA3dInputClassification inputSlotClass;
+ uint32 instanceDataStepRate;
+ uint32 inputRegister;
+} SVGA3dInputElementDesc;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 elid;
+ uint32 numDescs;
+ SVGA3dInputElementDesc descs[32];
+ uint32 pad[62];
+} SVGACOTableDXElementLayoutEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineElementLayout {
+ SVGA3dElementLayoutId elementLayoutId;
+
+} SVGA3dCmdDXDefineElementLayout;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyElementLayout {
+ SVGA3dElementLayoutId elementLayoutId;
+} SVGA3dCmdDXDestroyElementLayout;
+#pragma pack(pop)
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dDXBlendStatePerRT {
- uint8 blendEnable;
- uint8 srcBlend;
- uint8 destBlend;
- uint8 blendOp;
- uint8 srcBlendAlpha;
- uint8 destBlendAlpha;
- uint8 blendOpAlpha;
- SVGA3dColorWriteEnable renderTargetWriteMask;
- uint8 logicOpEnable;
- uint8 logicOp;
- uint16 pad0;
-}
-#include "vmware_pack_end.h"
-SVGA3dDXBlendStatePerRT;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint8 alphaToCoverageEnable;
- uint8 independentBlendEnable;
- uint16 pad0;
- SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
- uint32 pad1[7];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXBlendStateEntry;
-
-/*
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineBlendState {
- SVGA3dBlendStateId blendId;
- uint8 alphaToCoverageEnable;
- uint8 independentBlendEnable;
- uint16 pad0;
- SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineBlendState; /* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyBlendState {
- SVGA3dBlendStateId blendId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyBlendState; /* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint8 depthEnable;
- SVGA3dDepthWriteMask depthWriteMask;
- SVGA3dComparisonFunc depthFunc;
- uint8 stencilEnable;
- uint8 frontEnable;
- uint8 backEnable;
- uint8 stencilReadMask;
- uint8 stencilWriteMask;
-
- uint8 frontStencilFailOp;
- uint8 frontStencilDepthFailOp;
- uint8 frontStencilPassOp;
- SVGA3dComparisonFunc frontStencilFunc;
-
- uint8 backStencilFailOp;
- uint8 backStencilDepthFailOp;
- uint8 backStencilPassOp;
- SVGA3dComparisonFunc backStencilFunc;
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXDepthStencilEntry;
-
-/*
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineDepthStencilState {
- SVGA3dDepthStencilStateId depthStencilId;
-
- uint8 depthEnable;
- SVGA3dDepthWriteMask depthWriteMask;
- SVGA3dComparisonFunc depthFunc;
- uint8 stencilEnable;
- uint8 frontEnable;
- uint8 backEnable;
- uint8 stencilReadMask;
- uint8 stencilWriteMask;
-
- uint8 frontStencilFailOp;
- uint8 frontStencilDepthFailOp;
- uint8 frontStencilPassOp;
- SVGA3dComparisonFunc frontStencilFunc;
-
- uint8 backStencilFailOp;
- uint8 backStencilDepthFailOp;
- uint8 backStencilPassOp;
- SVGA3dComparisonFunc backStencilFunc;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineDepthStencilState;
-/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyDepthStencilState {
- SVGA3dDepthStencilStateId depthStencilId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyDepthStencilState;
-/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint8 fillMode;
- SVGA3dCullMode cullMode;
- uint8 frontCounterClockwise;
- uint8 provokingVertexLast;
- int32 depthBias;
- float depthBiasClamp;
- float slopeScaledDepthBias;
- uint8 depthClipEnable;
- uint8 scissorEnable;
- SVGA3dMultisampleRastEnable multisampleEnable;
- uint8 antialiasedLineEnable;
- float lineWidth;
- uint8 lineStippleEnable;
- uint8 lineStippleFactor;
- uint16 lineStipplePattern;
- uint8 forcedSampleCount;
- uint8 mustBeZero[3];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXRasterizerStateEntry;
-
-/*
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineRasterizerState {
- SVGA3dRasterizerStateId rasterizerId;
-
- uint8 fillMode;
- SVGA3dCullMode cullMode;
- uint8 frontCounterClockwise;
- uint8 provokingVertexLast;
- int32 depthBias;
- float depthBiasClamp;
- float slopeScaledDepthBias;
- uint8 depthClipEnable;
- uint8 scissorEnable;
- SVGA3dMultisampleRastEnable multisampleEnable;
- uint8 antialiasedLineEnable;
- float lineWidth;
- uint8 lineStippleEnable;
- uint8 lineStippleFactor;
- uint16 lineStipplePattern;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineRasterizerState;
-/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyRasterizerState {
- SVGA3dRasterizerStateId rasterizerId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyRasterizerState;
-/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGA3dFilter filter;
- uint8 addressU;
- uint8 addressV;
- uint8 addressW;
- uint8 pad0;
- float mipLODBias;
- uint8 maxAnisotropy;
- SVGA3dComparisonFunc comparisonFunc;
- uint16 pad1;
- SVGA3dRGBAFloat borderColor;
- float minLOD;
- float maxLOD;
- uint32 pad2[6];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXSamplerEntry;
-
-/*
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineSamplerState {
- SVGA3dSamplerId samplerId;
- SVGA3dFilter filter;
- uint8 addressU;
- uint8 addressV;
- uint8 addressW;
- uint8 pad0;
- float mipLODBias;
- uint8 maxAnisotropy;
- SVGA3dComparisonFunc comparisonFunc;
- uint16 pad1;
- SVGA3dRGBAFloat borderColor;
- float minLOD;
- float maxLOD;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineSamplerState; /* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroySamplerState {
- SVGA3dSamplerId samplerId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
-
-
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
-#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23
+#pragma pack(push, 1)
+typedef struct SVGA3dDXBlendStatePerRT {
+ uint8 blendEnable;
+ uint8 srcBlend;
+ uint8 destBlend;
+ uint8 blendOp;
+ uint8 srcBlendAlpha;
+ uint8 destBlendAlpha;
+ uint8 blendOpAlpha;
+ SVGA3dColorWriteEnable renderTargetWriteMask;
+ uint8 logicOpEnable;
+ uint8 logicOp;
+ uint16 pad0;
+} SVGA3dDXBlendStatePerRT;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint8 alphaToCoverageEnable;
+ uint8 independentBlendEnable;
+ uint16 pad0;
+ SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS];
+ uint32 pad1[7];
+} SVGACOTableDXBlendStateEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineBlendState {
+ SVGA3dBlendStateId blendId;
+ uint8 alphaToCoverageEnable;
+ uint8 independentBlendEnable;
+ uint16 pad0;
+ SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS];
+} SVGA3dCmdDXDefineBlendState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyBlendState {
+ SVGA3dBlendStateId blendId;
+} SVGA3dCmdDXDestroyBlendState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint8 depthEnable;
+ SVGA3dDepthWriteMask depthWriteMask;
+ SVGA3dComparisonFunc depthFunc;
+ uint8 stencilEnable;
+ uint8 frontEnable;
+ uint8 backEnable;
+ uint8 stencilReadMask;
+ uint8 stencilWriteMask;
+
+ uint8 frontStencilFailOp;
+ uint8 frontStencilDepthFailOp;
+ uint8 frontStencilPassOp;
+ SVGA3dComparisonFunc frontStencilFunc;
+
+ uint8 backStencilFailOp;
+ uint8 backStencilDepthFailOp;
+ uint8 backStencilPassOp;
+ SVGA3dComparisonFunc backStencilFunc;
+} SVGACOTableDXDepthStencilEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineDepthStencilState {
+ SVGA3dDepthStencilStateId depthStencilId;
+
+ uint8 depthEnable;
+ SVGA3dDepthWriteMask depthWriteMask;
+ SVGA3dComparisonFunc depthFunc;
+ uint8 stencilEnable;
+ uint8 frontEnable;
+ uint8 backEnable;
+ uint8 stencilReadMask;
+ uint8 stencilWriteMask;
+
+ uint8 frontStencilFailOp;
+ uint8 frontStencilDepthFailOp;
+ uint8 frontStencilPassOp;
+ SVGA3dComparisonFunc frontStencilFunc;
+
+ uint8 backStencilFailOp;
+ uint8 backStencilDepthFailOp;
+ uint8 backStencilPassOp;
+ SVGA3dComparisonFunc backStencilFunc;
+} SVGA3dCmdDXDefineDepthStencilState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyDepthStencilState {
+ SVGA3dDepthStencilStateId depthStencilId;
+} SVGA3dCmdDXDestroyDepthStencilState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint8 fillMode;
+ SVGA3dCullMode cullMode;
+ uint8 frontCounterClockwise;
+ uint8 provokingVertexLast;
+ int32 depthBias;
+ float depthBiasClamp;
+ float slopeScaledDepthBias;
+ uint8 depthClipEnable;
+ uint8 scissorEnable;
+ SVGA3dMultisampleRastEnable multisampleEnable;
+ uint8 antialiasedLineEnable;
+ float lineWidth;
+ uint8 lineStippleEnable;
+ uint8 lineStippleFactor;
+ uint16 lineStipplePattern;
+ uint8 forcedSampleCount;
+ uint8 mustBeZero[3];
+} SVGACOTableDXRasterizerStateEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineRasterizerState {
+ SVGA3dRasterizerStateId rasterizerId;
+
+ uint8 fillMode;
+ SVGA3dCullMode cullMode;
+ uint8 frontCounterClockwise;
+ uint8 provokingVertexLast;
+ int32 depthBias;
+ float depthBiasClamp;
+ float slopeScaledDepthBias;
+ uint8 depthClipEnable;
+ uint8 scissorEnable;
+ SVGA3dMultisampleRastEnable multisampleEnable;
+ uint8 antialiasedLineEnable;
+ float lineWidth;
+ uint8 lineStippleEnable;
+ uint8 lineStippleFactor;
+ uint16 lineStipplePattern;
+} SVGA3dCmdDXDefineRasterizerState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineRasterizerState_v2 {
+ SVGA3dRasterizerStateId rasterizerId;
+
+ uint8 fillMode;
+ SVGA3dCullMode cullMode;
+ uint8 frontCounterClockwise;
+ uint8 provokingVertexLast;
+ int32 depthBias;
+ float depthBiasClamp;
+ float slopeScaledDepthBias;
+ uint8 depthClipEnable;
+ uint8 scissorEnable;
+ SVGA3dMultisampleRastEnable multisampleEnable;
+ uint8 antialiasedLineEnable;
+ float lineWidth;
+ uint8 lineStippleEnable;
+ uint8 lineStippleFactor;
+ uint16 lineStipplePattern;
+ uint32 forcedSampleCount;
+} SVGA3dCmdDXDefineRasterizerState_v2;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyRasterizerState {
+ SVGA3dRasterizerStateId rasterizerId;
+} SVGA3dCmdDXDestroyRasterizerState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGA3dFilter filter;
+ uint8 addressU;
+ uint8 addressV;
+ uint8 addressW;
+ uint8 pad0;
+ float mipLODBias;
+ uint8 maxAnisotropy;
+ SVGA3dComparisonFunc comparisonFunc;
+ uint16 pad1;
+ SVGA3dRGBAFloat borderColor;
+ float minLOD;
+ float maxLOD;
+ uint32 pad2[6];
+} SVGACOTableDXSamplerEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineSamplerState {
+ SVGA3dSamplerId samplerId;
+ SVGA3dFilter filter;
+ uint8 addressU;
+ uint8 addressV;
+ uint8 addressW;
+ uint8 pad0;
+ float mipLODBias;
+ uint8 maxAnisotropy;
+ SVGA3dComparisonFunc comparisonFunc;
+ uint16 pad1;
+ SVGA3dRGBAFloat borderColor;
+ float minLOD;
+ float maxLOD;
+} SVGA3dCmdDXDefineSamplerState;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroySamplerState {
+ SVGA3dSamplerId samplerId;
+} SVGA3dCmdDXDestroySamplerState;
+#pragma pack(pop)
+
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
+#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23
typedef uint32 SVGA3dDXSignatureSemanticName;
#define SVGADX_SIGNATURE_REGISTER_COMPONENT_UNKNOWN 0
@@ -1670,398 +1394,331 @@ typedef uint32 SVGA3dDXSignatureRegisterComponentType;
#define SVGADX_SIGNATURE_MIN_PRECISION_DEFAULT 0
typedef uint32 SVGA3dDXSignatureMinPrecision;
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dDXSignatureEntry {
- uint32 registerIndex;
- SVGA3dDXSignatureSemanticName semanticName;
- uint32 mask; /* Lower 4 bits represent X, Y, Z, W channels */
- SVGA3dDXSignatureRegisterComponentType componentType;
- SVGA3dDXSignatureMinPrecision minPrecision;
-}
-#include "vmware_pack_end.h"
-SVGA3dDXShaderSignatureEntry;
+#pragma pack(push, 1)
+typedef struct SVGA3dDXSignatureEntry {
+ uint32 registerIndex;
+ SVGA3dDXSignatureSemanticName semanticName;
+ uint32 mask;
+ SVGA3dDXSignatureRegisterComponentType componentType;
+ SVGA3dDXSignatureMinPrecision minPrecision;
+} SVGA3dDXShaderSignatureEntry;
+#pragma pack(pop)
#define SVGADX_SIGNATURE_HEADER_VERSION_0 0x08a92d12
-/*
- * The SVGA3dDXSignatureHeader structure is added after the shader
- * body in the mob that is bound to the shader. It is followed by the
- * specified number of SVGA3dDXSignatureEntry structures for each of
- * the three types of signatures in the order (input, output, patch
- * constants).
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dDXSignatureHeader {
- uint32 headerVersion;
- uint32 numInputSignatures;
- uint32 numOutputSignatures;
- uint32 numPatchConstantSignatures;
-}
-#include "vmware_pack_end.h"
-SVGA3dDXShaderSignatureHeader;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineShader {
- SVGA3dShaderId shaderId;
- SVGA3dShaderType type;
- uint32 sizeInBytes; /* Number of bytes of shader text. */
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineShader; /* SVGA_3D_CMD_DX_DEFINE_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGACOTableDXShaderEntry {
- SVGA3dShaderType type;
- uint32 sizeInBytes;
- uint32 offsetInBytes;
- SVGAMobId mobid;
- uint32 pad[4];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXShaderEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyShader {
- SVGA3dShaderId shaderId;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyShader; /* SVGA_3D_CMD_DX_DESTROY_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindShader {
- uint32 cid;
- uint32 shid;
- SVGAMobId mobid;
- uint32 offsetInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindAllShader {
- uint32 cid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindAllShader; /* SVGA_3D_CMD_DX_BIND_ALL_SHADER */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXCondBindAllShader {
- uint32 cid;
- SVGAMobId testMobid;
- SVGAMobId mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXCondBindAllShader; /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER */
+#pragma pack(push, 1)
+typedef struct SVGA3dDXSignatureHeader {
+ uint32 headerVersion;
+ uint32 numInputSignatures;
+ uint32 numOutputSignatures;
+ uint32 numPatchConstantSignatures;
+} SVGA3dDXShaderSignatureHeader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineShader {
+ SVGA3dShaderId shaderId;
+ SVGA3dShaderType type;
+ uint32 sizeInBytes;
+} SVGA3dCmdDXDefineShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGACOTableDXShaderEntry {
+ SVGA3dShaderType type;
+ uint32 sizeInBytes;
+ uint32 offsetInBytes;
+ SVGAMobId mobid;
+ uint32 pad[4];
+} SVGACOTableDXShaderEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyShader {
+ SVGA3dShaderId shaderId;
+} SVGA3dCmdDXDestroyShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindShader {
+ uint32 cid;
+ uint32 shid;
+ SVGAMobId mobid;
+ uint32 offsetInBytes;
+} SVGA3dCmdDXBindShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindAllShader {
+ uint32 cid;
+ SVGAMobId mobid;
+} SVGA3dCmdDXBindAllShader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXCondBindAllShader {
+ uint32 cid;
+ SVGAMobId testMobid;
+ SVGAMobId mobid;
+} SVGA3dCmdDXCondBindAllShader;
+#pragma pack(pop)
-/*
- * The maximum number of streamout decl's in each streamout entry.
- */
#define SVGA3D_MAX_DX10_STREAMOUT_DECLS 64
#define SVGA3D_MAX_STREAMOUT_DECLS 512
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dStreamOutputDeclarationEntry {
- uint32 outputSlot;
- uint32 registerIndex;
- uint8 registerMask;
- uint8 pad0;
- uint16 pad1;
- uint32 stream;
-}
-#include "vmware_pack_end.h"
-SVGA3dStreamOutputDeclarationEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAOTableStreamOutputEntry {
- uint32 numOutputStreamEntries;
- SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
- uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
- uint32 rasterizedStream;
- uint32 numOutputStreamStrides;
- uint32 mobid;
- uint32 offsetInBytes;
- uint8 usesMob;
- uint8 pad0;
- uint16 pad1;
- uint32 pad2[246];
-}
-#include "vmware_pack_end.h"
-SVGACOTableDXStreamOutputEntry;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineStreamOutput {
- SVGA3dStreamOutputId soid;
- uint32 numOutputStreamEntries;
- SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
- uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
- uint32 rasterizedStream;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineStreamOutput; /* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT */
-
-/*
- * Version 2 needed in order to start validating and using the
- * rasterizedStream field. Unfortunately the device wasn't validating
- * or using this field and the driver wasn't initializing it in shipped
- * code, so a new version of the command is needed to allow that code
- * to continue to work. Also added new numOutputStreamStrides field.
- */
+#pragma pack(push, 1)
+typedef struct SVGA3dStreamOutputDeclarationEntry {
+ uint32 outputSlot;
+ uint32 registerIndex;
+ uint8 registerMask;
+ uint8 pad0;
+ uint16 pad1;
+ uint32 stream;
+} SVGA3dStreamOutputDeclarationEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGAOTableStreamOutputEntry {
+ uint32 numOutputStreamEntries;
+ SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
+ uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
+ uint32 rasterizedStream;
+ uint32 numOutputStreamStrides;
+ uint32 mobid;
+ uint32 offsetInBytes;
+ uint8 usesMob;
+ uint8 pad0;
+ uint16 pad1;
+ uint32 pad2[246];
+} SVGACOTableDXStreamOutputEntry;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineStreamOutput {
+ SVGA3dStreamOutputId soid;
+ uint32 numOutputStreamEntries;
+ SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
+ uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
+ uint32 rasterizedStream;
+} SVGA3dCmdDXDefineStreamOutput;
+#pragma pack(pop)
#define SVGA3D_DX_SO_NO_RASTERIZED_STREAM 0xFFFFFFFF
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDefineStreamOutputWithMob {
- SVGA3dStreamOutputId soid;
- uint32 numOutputStreamEntries;
- uint32 numOutputStreamStrides;
- uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
- uint32 rasterizedStream;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDefineStreamOutputWithMob;
-/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXBindStreamOutput {
- SVGA3dStreamOutputId soid;
- uint32 mobid;
- uint32 offsetInBytes;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXBindStreamOutput; /* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXDestroyStreamOutput {
- SVGA3dStreamOutputId soid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXDestroyStreamOutput; /* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetStreamOutput {
- SVGA3dStreamOutputId soid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetStreamOutput; /* SVGA_3D_CMD_DX_SET_STREAMOUTPUT */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetMinLOD {
- SVGA3dSurfaceId sid;
- float minLOD;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetMinLOD; /* SVGA_3D_CMD_DX_SET_MIN_LOD */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 value;
- uint32 mobId;
- uint32 mobOffset;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDefineStreamOutputWithMob {
+ SVGA3dStreamOutputId soid;
+ uint32 numOutputStreamEntries;
+ uint32 numOutputStreamStrides;
+ uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
+ uint32 rasterizedStream;
+} SVGA3dCmdDXDefineStreamOutputWithMob;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXBindStreamOutput {
+ SVGA3dStreamOutputId soid;
+ uint32 mobid;
+ uint32 offsetInBytes;
+ uint32 sizeInBytes;
+} SVGA3dCmdDXBindStreamOutput;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXDestroyStreamOutput {
+ SVGA3dStreamOutputId soid;
+} SVGA3dCmdDXDestroyStreamOutput;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetStreamOutput {
+ SVGA3dStreamOutputId soid;
+} SVGA3dCmdDXSetStreamOutput;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetMinLOD {
+ SVGA3dSurfaceId sid;
+ float minLOD;
+} SVGA3dCmdDXSetMinLOD;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 value;
+ uint32 mobId;
+ uint32 mobOffset;
+} SVGA3dCmdDXMobFence64;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXSetCOTable {
+ uint32 cid;
+ uint32 mobid;
+ SVGACOTableType type;
+ uint32 validSizeInBytes;
+} SVGA3dCmdDXSetCOTable;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXGrowCOTable {
+ uint32 cid;
+ uint32 mobid;
+ SVGACOTableType type;
+ uint32 validSizeInBytes;
+} SVGA3dCmdDXGrowCOTable;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXReadbackCOTable {
+ uint32 cid;
+ SVGACOTableType type;
+} SVGA3dCmdDXReadbackCOTable;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXCopyCOTableIntoMob {
+ uint32 cid;
+ SVGACOTableType type;
+ uint32 mobid;
+} SVGA3dCmdDXCopyCOTableIntoMob;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXPredStagingCopy {
+ SVGA3dSurfaceId dstSid;
+ SVGA3dSurfaceId srcSid;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+
+} SVGA3dCmdDXPredStagingCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCmdDXStagingCopy {
+ SVGA3dSurfaceId dstSid;
+ SVGA3dSurfaceId srcSid;
+ uint8 readback;
+ uint8 unsynchronized;
+ uint8 mustBeZero[2];
+
+} SVGA3dCmdDXStagingCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCOTableData {
+ uint32 mobid;
+} SVGA3dCOTableData;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dBufferBinding {
+ uint32 bufferId;
+ uint32 stride;
+ uint32 offset;
+} SVGA3dBufferBinding;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dConstantBufferBinding {
+ uint32 sid;
+ uint32 offsetInBytes;
+ uint32 sizeInBytes;
+} SVGA3dConstantBufferBinding;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGADXInputAssemblyMobFormat {
+ uint32 layoutId;
+ SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
+ uint32 indexBufferSid;
+ uint32 pad;
+ uint32 indexBufferOffset;
+ uint32 indexBufferFormat;
+ uint32 topology;
+} SVGADXInputAssemblyMobFormat;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGADXContextMobFormat {
+ SVGADXInputAssemblyMobFormat inputAssembly;
+
+ struct {
+ uint32 blendStateId;
+ uint32 blendFactor[4];
+ uint32 sampleMask;
+ uint32 depthStencilStateId;
+ uint32 stencilRef;
+ uint32 rasterizerStateId;
+ uint32 depthStencilViewId;
+ uint32 renderTargetViewIds[SVGA3D_DX_MAX_RENDER_TARGETS];
+ } renderState;
+
+ uint32 pad0[8];
+
+ struct {
+ uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
+ uint32 soid;
+ } streamOut;
+
+ uint32 pad1[10];
+
+ uint32 uavSpliceIndex;
+
+ uint8 numViewports;
+ uint8 numScissorRects;
+ uint16 pad2[1];
+
+ uint32 pad3[3];
+
+ SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
+ uint32 pad4[32];
+
+ SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
+ uint32 pad5[64];
+
+ struct {
+ uint32 queryID;
+ uint32 value;
+ } predication;
+
+ SVGAMobId shaderIfaceMobid;
+ uint32 shaderIfaceOffset;
+ struct {
+ uint32 shaderId;
+ SVGA3dConstantBufferBinding
+ constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
+ uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
+ uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
+ } shaderState[SVGA3D_NUM_SHADERTYPE];
+ uint32 pad6[26];
+
+ SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
+
+ SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
+
+ uint32 pad7[64];
+
+ uint32 uaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
+ uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
+
+ uint32 pad8[188];
+} SVGADXContextMobFormat;
+#pragma pack(pop)
-/*
- * SVGA3dCmdSetCOTable --
- *
- * This command allows the guest to bind a mob to a context-object table.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXSetCOTable {
- uint32 cid;
- uint32 mobid;
- SVGACOTableType type;
- uint32 validSizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
+#define SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED 256
-/*
- * Guests using SVGA_3D_CMD_DX_GROW_COTABLE are promising that
- * the new COTable contains the same contents as the old one, except possibly
- * for some new invalid entries at the end.
- *
- * If there is an old cotable mob bound, it also has to still be valid.
- *
- * (Otherwise, guests should use the DXSetCOTableBase command.)
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXGrowCOTable {
- uint32 cid;
- uint32 mobid;
- SVGACOTableType type;
- uint32 validSizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXGrowCOTable; /* SVGA_3D_CMD_DX_GROW_COTABLE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXReadbackCOTable {
- uint32 cid;
- SVGACOTableType type;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXReadbackCOTable; /* SVGA_3D_CMD_DX_READBACK_COTABLE */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCOTableData {
- uint32 mobid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCOTableData;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dBufferBinding {
- uint32 bufferId;
- uint32 stride;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGA3dBufferBinding;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dConstantBufferBinding {
- uint32 sid;
- uint32 offsetInBytes;
- uint32 sizeInBytes;
-}
-#include "vmware_pack_end.h"
-SVGA3dConstantBufferBinding;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGADXInputAssemblyMobFormat {
- uint32 layoutId;
- SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
- uint32 indexBufferSid;
- uint32 pad;
- uint32 indexBufferOffset;
- uint32 indexBufferFormat;
- uint32 topology;
-}
-#include "vmware_pack_end.h"
-SVGADXInputAssemblyMobFormat;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGADXContextMobFormat {
- SVGADXInputAssemblyMobFormat inputAssembly;
-
- struct {
- uint32 blendStateId;
- uint32 blendFactor[4];
- uint32 sampleMask;
- uint32 depthStencilStateId;
- uint32 stencilRef;
- uint32 rasterizerStateId;
- uint32 depthStencilViewId;
- uint32 renderTargetViewIds[SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS];
- } renderState;
-
- uint32 pad0[8];
-
- struct {
- uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
- uint32 soid;
- } streamOut;
-
- uint32 pad1[10];
-
- uint32 uavSpliceIndex;
-
- uint8 numViewports;
- uint8 numScissorRects;
- uint16 pad2[1];
-
- uint32 pad3[3];
-
- SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
- uint32 pad4[32];
-
- SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
- uint32 pad5[64];
-
- struct {
- uint32 queryID;
- uint32 value;
- } predication;
-
- SVGAMobId shaderIfaceMobid;
- uint32 shaderIfaceOffset;
- struct {
- uint32 shaderId;
- SVGA3dConstantBufferBinding constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
- uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
- uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
- } shaderState[SVGA3D_NUM_SHADERTYPE];
- uint32 pad6[26];
-
- SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
-
- SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
-
- uint32 pad7[64];
-
- uint32 uaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
- uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
-
- uint32 pad8[188];
-}
-#include "vmware_pack_end.h"
-SVGADXContextMobFormat;
+#pragma pack(push, 1)
+typedef struct SVGADXShaderIfaceMobFormat {
+ struct {
+ uint32 numClassInstances;
+ uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
+ SVGA3dIfaceData data[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
+ } shaderIfaceState[SVGA3D_NUM_SHADERTYPE];
-/*
- * There is conflicting documentation on max class instances (253 vs 256). The
- * lower value is the one used throughout the device, but since mob format is
- * more involved to increase if needed, conservatively use the higher one here.
- */
-#define SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED 256
+ uint32 pad0[1018];
+} SVGADXShaderIfaceMobFormat;
+#pragma pack(pop)
-typedef
-#include "vmware_pack_begin.h"
-struct SVGADXShaderIfaceMobFormat {
- struct {
- uint32 numClassInstances;
- uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
- SVGA3dIfaceData data[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
- } shaderIfaceState[SVGA3D_NUM_SHADERTYPE];
-
- uint32 pad0[1018];
-}
-#include "vmware_pack_end.h"
-SVGADXShaderIfaceMobFormat;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCmdDXTempSetContext {
- uint32 dxcid;
-}
-#include "vmware_pack_end.h"
-SVGA3dCmdDXTempSetContext; /* SVGA_3D_CMD_DX_TEMP_SET_CONTEXT */
-
-#endif /* _SVGA3D_DX_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
index f4375a41b3aaa152f508f93d335e97571f56bb74..35494a728c7a330e31dd41e60596c175c5176c9f 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2007-2019 VMware, Inc.
+ * Copyright 2012-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,104 +27,59 @@
/*
* svga3d_limits.h --
*
- * SVGA 3d hardware limits
+ * SVGA 3d hardware limits
*/
-#ifndef _SVGA3D_LIMITS_H_
-#define _SVGA3D_LIMITS_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
+#ifndef _SVGA3D_LIMITS_H_
+#define _SVGA3D_LIMITS_H_
-#define SVGA3D_NUM_CLIPPLANES 6
-#define SVGA3D_MAX_CONTEXT_IDS 256
-#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
+#define SVGA3D_HB_MAX_CONTEXT_IDS 256
+#define SVGA3D_HB_MAX_SURFACE_IDS (32 * 1024)
-/*
- * While there are separate bind-points for RenderTargetViews and
- * UnorderedAccessViews in a DXContext, there is in fact one shared
- * semantic space that the guest-driver can use on any given draw call.
- * So there are really only 8 slots that can be spilt up between them, with the
- * spliceIndex controlling where the UAV's sit in the collapsed array.
- */
-#define SVGA3D_MAX_RENDER_TARGETS 8
-#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
-#define SVGA3D_MAX_UAVIEWS 8
-#define SVGA3D_DX11_1_MAX_UAVIEWS 64
+#define SVGA3D_DX_MAX_RENDER_TARGETS 8
+#define SVGA3D_DX11_MAX_UAVIEWS 8
+#define SVGA3D_DX11_1_MAX_UAVIEWS 64
+#define SVGA3D_MAX_UAVIEWS (SVGA3D_DX11_1_MAX_UAVIEWS)
+#define SVGA3D_DX11_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_MAX_UAVIEWS)
+#define SVGA3D_DX11_1_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_1_MAX_UAVIEWS)
+#define SVGA3D_MAX_SIMULTANEOUS_RTUAV (SVGA3D_MAX_UAVIEWS)
-/*
- * Maximum canonical size of a surface in host-backed mode (pre-GBObjects).
- */
#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)
-/*
- * Maximum ID a shader can be assigned on a given context.
- */
-#define SVGA3D_MAX_SHADERIDS 5000
-/*
- * Maximum number of shaders of a given type that can be defined
- * (including all contexts).
- */
-#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
+#define SVGA3D_MAX_SHADERIDS 5000
-#define SVGA3D_NUM_TEXTURE_UNITS 32
-#define SVGA3D_NUM_LIGHTS 8
+#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
-#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
+#define SVGA3D_NUM_TEXTURE_UNITS 32
+#define SVGA3D_NUM_LIGHTS 8
+
+#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
-/*
- * Maximum size in dwords of shader text the SVGA device will allow.
- * Currently 8 MB.
- */
#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
-#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
- sizeof(uint32))
+#define SVGA3D_MAX_SHADER_MEMORY \
+ (SVGA3D_MAX_SHADER_MEMORY_BYTES / sizeof(uint32))
-/*
- * The maximum value of threadGroupCount in each dimension
- */
#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535
-#define SVGA3D_MAX_CLIP_PLANES 6
+#define SVGA3D_MAX_CLIP_PLANES 6
-/*
- * This is the limit to the number of fixed-function texture
- * transforms and texture coordinates we can support. It does *not*
- * correspond to the number of texture image units (samplers) we
- * support!
- */
#define SVGA3D_MAX_TEXTURE_COORDS 8
-/*
- * Number of faces in a cubemap.
- */
#define SVGA3D_MAX_SURFACE_FACES 6
-/*
- * Maximum number of array indexes in a GB surface (with DX enabled).
- */
#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
-/*
- * The maximum number of vertex arrays we're guaranteed to support in
- * SVGA_3D_CMD_DRAWPRIMITIVES.
- */
-#define SVGA3D_MAX_VERTEX_ARRAYS 32
+#define SVGA3D_MAX_VERTEX_ARRAYS 32
-/*
- * The maximum number of primitive ranges we're guaranteed to support
- * in SVGA_3D_CMD_DRAWPRIMITIVES.
- */
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
-/*
- * The maximum number of samples that can be contained in a surface.
- */
#define SVGA3D_MAX_SAMPLES 8
-#endif /* _SVGA3D_LIMITS_H_ */
+#define SVGA3D_MIN_SBX_DATA_SIZE (GBYTES_2_BYTES(1))
+#define SVGA3D_MAX_SBX_DATA_SIZE (GBYTES_2_BYTES(4))
+
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
index bdfc404c91e3ca3ce81c15a5ce8ad3c8d8a5c886..988d8509c4728e5a48902e906df24e693409b89f 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 1998-2015 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,17 +27,13 @@
/*
* svga3d_reg.h --
*
- * SVGA 3d hardware definitions
+ * SVGA 3d hardware definitions
*/
-#ifndef _SVGA3D_REG_H_
-#define _SVGA3D_REG_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
+#ifndef _SVGA3D_REG_H_
+#define _SVGA3D_REG_H_
#include "svga_reg.h"
@@ -47,5 +43,4 @@
#include "svga3d_dx.h"
#include "svga3d_devcaps.h"
-
-#endif /* _SVGA3D_REG_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
index 127eaf0a0a5803eb2ec5faa1631c827c669995b8..7d98fc48414e2c629929602305d39af315955899 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
@@ -1,1667 +1,1561 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
-/**************************************************************************
+/**********************************************************
+ * Copyright 2008-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
- * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
*
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
+ **********************************************************/
/*
* svga3d_surfacedefs.h --
*
- * Surface definitions and inlineable utilities for SVGA3d.
+ * Surface definitions for SVGA3d.
*/
+
+
#ifndef _SVGA3D_SURFACEDEFS_H_
#define _SVGA3D_SURFACEDEFS_H_
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_MODULE
-#include "includeCheck.h"
+#include "svga3d_types.h"
-#include <linux/kernel.h>
-#include <drm/vmwgfx_drm.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
-#include "svga3d_reg.h"
+struct SVGAUseCaps;
-#define surf_size_struct struct drm_vmw_size
+#if defined(_WIN32) && !defined(__GNUC__)
-/*
- * enum svga3d_block_desc - describes generic properties about formats.
- */
-enum svga3d_block_desc {
- /* Nothing special can be said about this format. */
- SVGA3DBLOCKDESC_NONE = 0,
+#define STATIC_CONST __declspec(selectany) extern const
+#else
+#define STATIC_CONST static const
+#endif
+
+typedef enum SVGA3dBlockDesc {
- /* Format contains Blue/U data */
- SVGA3DBLOCKDESC_BLUE = 1 << 0,
- SVGA3DBLOCKDESC_W = 1 << 0,
- SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
+ SVGA3DBLOCKDESC_NONE = 0,
- /* Format contains Green/V data */
- SVGA3DBLOCKDESC_GREEN = 1 << 1,
- SVGA3DBLOCKDESC_V = 1 << 1,
+ SVGA3DBLOCKDESC_BLUE = 1 << 0,
+ SVGA3DBLOCKDESC_W = 1 << 0,
+ SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
- /* Format contains Red/W/Luminance data */
- SVGA3DBLOCKDESC_RED = 1 << 2,
- SVGA3DBLOCKDESC_U = 1 << 2,
- SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
+ SVGA3DBLOCKDESC_GREEN = 1 << 1,
+ SVGA3DBLOCKDESC_V = 1 << 1,
- /* Format contains Alpha/Q data */
- SVGA3DBLOCKDESC_ALPHA = 1 << 3,
- SVGA3DBLOCKDESC_Q = 1 << 3,
+ SVGA3DBLOCKDESC_RED = 1 << 2,
+ SVGA3DBLOCKDESC_U = 1 << 2,
+ SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
- /* Format is a buffer */
- SVGA3DBLOCKDESC_BUFFER = 1 << 4,
+ SVGA3DBLOCKDESC_ALPHA = 1 << 3,
+ SVGA3DBLOCKDESC_Q = 1 << 3,
- /* Format is compressed */
- SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
+ SVGA3DBLOCKDESC_BUFFER = 1 << 4,
- /* Format uses IEEE floating point */
- SVGA3DBLOCKDESC_FP = 1 << 6,
+ SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
- /* Three separate blocks store data. */
- SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
+ SVGA3DBLOCKDESC_FP = 1 << 6,
+
+ SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
- /* 2 planes of Y, UV, e.g., NV12. */
SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8,
- /* 3 planes of separate Y, U, V, e.g., YV12. */
SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9,
- /* Block with a stencil channel */
- SVGA3DBLOCKDESC_STENCIL = 1 << 11,
-
- /* Typeless format */
- SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
-
- /* Channels are signed integers */
- SVGA3DBLOCKDESC_SINT = 1 << 13,
-
- /* Channels are unsigned integers */
- SVGA3DBLOCKDESC_UINT = 1 << 14,
-
- /* Channels are normalized (when sampling) */
- SVGA3DBLOCKDESC_NORM = 1 << 15,
-
- /* Channels are in SRGB */
- SVGA3DBLOCKDESC_SRGB = 1 << 16,
-
- /* Shared exponent */
- SVGA3DBLOCKDESC_EXP = 1 << 17,
-
- /* Format contains color data. */
- SVGA3DBLOCKDESC_COLOR = 1 << 18,
- /* Format contains depth data. */
- SVGA3DBLOCKDESC_DEPTH = 1 << 19,
- /* Format contains bump data. */
- SVGA3DBLOCKDESC_BUMP = 1 << 20,
-
- /* Format contains YUV video data. */
- SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
-
- /* For mixed unsigned/signed formats. */
- SVGA3DBLOCKDESC_MIXED = 1 << 22,
-
- /* For distingushing CxV8U8. */
- SVGA3DBLOCKDESC_CX = 1 << 23,
-
- /* Different compressed format groups. */
- SVGA3DBLOCKDESC_BC1 = 1 << 24,
- SVGA3DBLOCKDESC_BC2 = 1 << 25,
- SVGA3DBLOCKDESC_BC3 = 1 << 26,
- SVGA3DBLOCKDESC_BC4 = 1 << 27,
- SVGA3DBLOCKDESC_BC5 = 1 << 28,
- SVGA3DBLOCKDESC_BC6H = 1 << 29,
- SVGA3DBLOCKDESC_BC7 = 1 << 30,
-
- SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_FP |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
- SVGA3DBLOCKDESC_V |
- SVGA3DBLOCKDESC_BUMP,
- SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
- SVGA3DBLOCKDESC_BUMP_L |
- SVGA3DBLOCKDESC_MIXED |
- SVGA3DBLOCKDESC_BUMP,
- SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
- SVGA3DBLOCKDESC_W |
- SVGA3DBLOCKDESC_BUMP,
- SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
- SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_MIXED |
- SVGA3DBLOCKDESC_BUMP,
- SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
- SVGA3DBLOCKDESC_V |
- SVGA3DBLOCKDESC_W |
- SVGA3DBLOCKDESC_Q |
- SVGA3DBLOCKDESC_BUMP,
- SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_NORM |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
- SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_NORM |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_FP |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
- SVGA3DBLOCKDESC_YUV_VIDEO |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED |
- SVGA3DBLOCKDESC_GREEN |
- SVGA3DBLOCKDESC_BLUE |
- SVGA3DBLOCKDESC_EXP |
- SVGA3DBLOCKDESC_COLOR,
-
- SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED |
- SVGA3DBLOCKDESC_TYPELESS,
- SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED |
- SVGA3DBLOCKDESC_UINT |
- SVGA3DBLOCKDESC_NORM |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_NORM |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM |
- SVGA3DBLOCKDESC_SRGB,
- SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 |
- SVGA3DBLOCKDESC_COMP_SNORM,
- SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 |
- SVGA3DBLOCKDESC_COMP_SNORM,
- SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H |
- SVGA3DBLOCKDESC_COMPRESSED,
- SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H |
- SVGA3DBLOCKDESC_COMPRESSED,
- SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 |
- SVGA3DBLOCKDESC_COMP_TYPELESS,
- SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 |
- SVGA3DBLOCKDESC_COMP_UNORM,
- SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM |
- SVGA3DBLOCKDESC_SRGB,
-
- SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
- SVGA3DBLOCKDESC_PLANAR_YUV |
- SVGA3DBLOCKDESC_2PLANAR_YUV |
- SVGA3DBLOCKDESC_COLOR,
- SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
- SVGA3DBLOCKDESC_PLANAR_YUV |
- SVGA3DBLOCKDESC_3PLANAR_YUV |
- SVGA3DBLOCKDESC_COLOR,
-
- SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH |
- SVGA3DBLOCKDESC_UINT,
- SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
- SVGA3DBLOCKDESC_STENCIL,
- SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH |
- SVGA3DBLOCKDESC_STENCIL |
- SVGA3DBLOCKDESC_UINT,
- SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH |
- SVGA3DBLOCKDESC_FP,
-
- SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV |
- SVGA3DBLOCKDESC_UINT,
- SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV |
- SVGA3DBLOCKDESC_SINT |
- SVGA3DBLOCKDESC_NORM,
- SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM |
- SVGA3DBLOCKDESC_CX,
+ SVGA3DBLOCKDESC_STENCIL = 1 << 11,
+
+ SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
+
+ SVGA3DBLOCKDESC_SINT = 1 << 13,
+
+ SVGA3DBLOCKDESC_UINT = 1 << 14,
+
+ SVGA3DBLOCKDESC_NORM = 1 << 15,
+
+ SVGA3DBLOCKDESC_SRGB = 1 << 16,
+
+ SVGA3DBLOCKDESC_EXP = 1 << 17,
+
+ SVGA3DBLOCKDESC_COLOR = 1 << 18,
+
+ SVGA3DBLOCKDESC_DEPTH = 1 << 19,
+
+ SVGA3DBLOCKDESC_BUMP = 1 << 20,
+
+ SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
+
+ SVGA3DBLOCKDESC_MIXED = 1 << 22,
+
+ SVGA3DBLOCKDESC_CX = 1 << 23,
+
+ SVGA3DBLOCKDESC_BC1 = 1 << 24,
+ SVGA3DBLOCKDESC_BC2 = 1 << 25,
+ SVGA3DBLOCKDESC_BC3 = 1 << 26,
+ SVGA3DBLOCKDESC_BC4 = 1 << 27,
+ SVGA3DBLOCKDESC_BC5 = 1 << 28,
+ SVGA3DBLOCKDESC_BC6H = 1 << 29,
+ SVGA3DBLOCKDESC_BC7 = 1 << 30,
+ SVGA3DBLOCKDESC_COMPRESSED_MASK =
+ SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_BC2 |
+ SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_BC4 |
+ SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_BC6H |
+ SVGA3DBLOCKDESC_BC7,
+
+ SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | SVGA3DBLOCKDESC_UINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_UINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_SINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | SVGA3DBLOCKDESC_UINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RG_UNORM =
+ SVGA3DBLOCKDESC_RG_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RG_SNORM =
+ SVGA3DBLOCKDESC_RG_SINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_UINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_SINT |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGB_UNORM =
+ SVGA3DBLOCKDESC_RGB_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_RGB_UNORM_SRGB =
+ SVGA3DBLOCKDESC_RGB_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_RGBA_UINT =
+ SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGBA_UNORM =
+ SVGA3DBLOCKDESC_RGBA_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM_SRGB =
+ SVGA3DBLOCKDESC_RGBA_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_RGBA_SINT =
+ SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGBA_SNORM =
+ SVGA3DBLOCKDESC_RGBA_SINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_FP | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_UV =
+ SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V | SVGA3DBLOCKDESC_BUMP,
+ SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_BUMP_L |
+ SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP,
+ SVGA3DBLOCKDESC_UVW =
+ SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_BUMP,
+ SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP,
+ SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V |
+ SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_Q |
+ SVGA3DBLOCKDESC_BUMP,
+ SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
+ SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_NORM |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
+ SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_NORM |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_FP |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | SVGA3DBLOCKDESC_BLUE |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
+ SVGA3DBLOCKDESC_YUV_VIDEO |
+ SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
+ SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_EXP |
+ SVGA3DBLOCKDESC_COLOR,
+
+ SVGA3DBLOCKDESC_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_TYPELESS,
+ SVGA3DBLOCKDESC_COMP_UNORM =
+ SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_UINT |
+ SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_COMP_SNORM =
+ SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_SINT |
+ SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_COMP_UNORM_SRGB =
+ SVGA3DBLOCKDESC_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_BC1_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB =
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_BC2_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB =
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_BC3_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB =
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
+ SVGA3DBLOCKDESC_BC4_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC4_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC4_COMP_SNORM =
+ SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_SNORM,
+ SVGA3DBLOCKDESC_BC5_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC5_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC5_COMP_SNORM =
+ SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_SNORM,
+ SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC6H_COMP_UF16 =
+ SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED,
+ SVGA3DBLOCKDESC_BC6H_COMP_SF16 =
+ SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED,
+ SVGA3DBLOCKDESC_BC7_COMP_TYPELESS =
+ SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_TYPELESS,
+ SVGA3DBLOCKDESC_BC7_COMP_UNORM =
+ SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_UNORM,
+ SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB =
+ SVGA3DBLOCKDESC_BC7_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
+
+ SVGA3DBLOCKDESC_NV12 =
+ SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_PLANAR_YUV |
+ SVGA3DBLOCKDESC_2PLANAR_YUV | SVGA3DBLOCKDESC_COLOR,
+ SVGA3DBLOCKDESC_YV12 =
+ SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_PLANAR_YUV |
+ SVGA3DBLOCKDESC_3PLANAR_YUV | SVGA3DBLOCKDESC_COLOR,
+
+ SVGA3DBLOCKDESC_DEPTH_UINT =
+ SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_UINT,
+ SVGA3DBLOCKDESC_DEPTH_UNORM =
+ SVGA3DBLOCKDESC_DEPTH_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_STENCIL,
+ SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH |
+ SVGA3DBLOCKDESC_STENCIL |
+ SVGA3DBLOCKDESC_UINT,
+ SVGA3DBLOCKDESC_DS_UNORM =
+ SVGA3DBLOCKDESC_DS_UINT | SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_FP,
+
+ SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_UINT,
+ SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_SINT |
+ SVGA3DBLOCKDESC_NORM,
+ SVGA3DBLOCKDESC_UVCX_SNORM =
+ SVGA3DBLOCKDESC_UV_SNORM | SVGA3DBLOCKDESC_CX,
SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ |
SVGA3DBLOCKDESC_SINT |
SVGA3DBLOCKDESC_NORM,
-};
+} SVGA3dBlockDesc;
-struct svga3d_channel_def {
+typedef struct SVGA3dChannelDef {
union {
- u8 blue;
- u8 w_bump;
- u8 l_bump;
- u8 uv_video;
- u8 u_video;
+ uint8 blue;
+ uint8 w_bump;
+ uint8 l_bump;
+ uint8 uv_video;
+ uint8 u_video;
};
union {
- u8 green;
- u8 stencil;
- u8 v_bump;
- u8 v_video;
+ uint8 green;
+ uint8 stencil;
+ uint8 v_bump;
+ uint8 v_video;
};
union {
- u8 red;
- u8 u_bump;
- u8 luminance;
- u8 y_video;
- u8 depth;
- u8 data;
+ uint8 red;
+ uint8 u_bump;
+ uint8 luminance;
+ uint8 y_video;
+ uint8 depth;
+ uint8 data;
};
union {
- u8 alpha;
- u8 q_bump;
- u8 exp;
+ uint8 alpha;
+ uint8 q_bump;
+ uint8 exp;
};
-};
+} SVGA3dChannelDef;
-/*
- * struct svga3d_surface_desc - describes the actual pixel data.
- *
- * @format: Format
- * @block_desc: Block description
- * @block_size: Dimensions in pixels of a block
- * @bytes_per_block: Size of block in bytes
- * @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch
- * @bit_depth: Channel bit depths
- * @bit_offset: Channel bit masks (in bits offset from the start of the pointer)
- */
-struct svga3d_surface_desc {
+typedef struct SVGA3dSurfaceDesc {
SVGA3dSurfaceFormat format;
- enum svga3d_block_desc block_desc;
-
- surf_size_struct block_size;
- u32 bytes_per_block;
- u32 pitch_bytes_per_block;
-
- struct svga3d_channel_def bit_depth;
- struct svga3d_channel_def bit_offset;
-};
-
-static const struct svga3d_surface_desc svga3d_surface_descs[] = {
- {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
- {1, 1, 1}, 0, 0,
- {{0}, {0}, {0}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM,
- {1, 1, 1}, 2, 2,
- {{5}, {6}, {5}, {0}},
- {{0}, {5}, {11}, {0}}},
-
- {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM,
- {1, 1, 1}, 2, 2,
- {{5}, {5}, {5}, {0}},
- {{0}, {5}, {10}, {0}}},
-
- {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 2, 2,
- {{5}, {5}, {5}, {1}},
- {{0}, {5}, {10}, {15}}},
-
- {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 2, 2,
- {{4}, {4}, {4}, {4}},
- {{0}, {4}, {8}, {12}}},
-
- {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {8}, {24}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {1}, {15}, {0}},
- {{0}, {0}, {1}, {0}}},
-
- {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {4}, {4}},
- {{0}, {0}, {0}, {4}}},
-
- {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {8}, {8}},
- {{0}, {0}, {0}, {8}}},
-
- {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
- {1, 1, 1}, 2, 2,
- {{6}, {5}, {5}, {0}},
- {{10}, {5}, {0}, {0}}},
-
- {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{16}, {8}, {0}, {0}}},
-
- {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE,
- {1, 1, 1}, 3, 3,
- {{8}, {8}, {8}, {0}},
- {{16}, {8}, {0}, {0}}},
-
- {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
- {1, 1, 1}, 16, 16,
- {{32}, {32}, {32}, {32}},
- {{64}, {32}, {0}, {96}}},
-
- {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{0}, {10}, {20}, {30}}},
-
- {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{16}, {8}, {0}, {0}}},
-
- {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{20}, {10}, {0}, {30}}},
-
- {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {0}, {8}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
- {1, 1, 1}, 8, 8,
- {{0}, {32}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {24}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
- {2, 1, 1}, 4, 4,
- {{8}, {0}, {8}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
- {2, 1, 1}, 4, 4,
- {{8}, {0}, {8}, {0}},
- {{8}, {0}, {0}, {0}}},
-
- {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
- {2, 2, 1}, 6, 2,
- {{0}, {0}, {48}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 16, 16,
- {{32}, {32}, {32}, {32}},
- {{64}, {32}, {0}, {96}}},
-
- {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
- {1, 1, 1}, 16, 16,
- {{32}, {32}, {32}, {32}},
- {{64}, {32}, {0}, {96}}},
-
- {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
- {1, 1, 1}, 16, 16,
- {{32}, {32}, {32}, {32}},
- {{64}, {32}, {0}, {96}}},
-
- {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 12, 12,
- {{32}, {32}, {32}, {0}},
- {{64}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
- {1, 1, 1}, 12, 12,
- {{32}, {32}, {32}, {0}},
- {{64}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT,
- {1, 1, 1}, 12, 12,
- {{32}, {32}, {32}, {0}},
- {{64}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT,
- {1, 1, 1}, 12, 12,
- {{32}, {32}, {32}, {0}},
- {{64}, {32}, {0}, {0}}},
-
- {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 8, 8,
- {{0}, {32}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT,
- {1, 1, 1}, 8, 8,
- {{0}, {32}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT,
- {1, 1, 1}, 8, 8,
- {{0}, {32}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 8, 8,
- {{0}, {8}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
- {1, 1, 1}, 8, 8,
- {{0}, {8}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP,
- {1, 1, 1}, 8, 8,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT,
- {1, 1, 1}, 8, 8,
- {{0}, {8}, {0}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{20}, {10}, {0}, {30}}},
-
- {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{20}, {10}, {0}, {30}}},
-
- {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
- {1, 1, 1}, 4, 4,
- {{10}, {11}, {11}, {0}},
- {{22}, {11}, {0}, {0}}},
-
- {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{0}, {8}, {24}, {0}},
- {{0}, {24}, {0}, {0}}},
-
- {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {8}, {24}, {0}},
- {{0}, {24}, {0}, {0}}},
-
- {SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {24}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT,
- {1, 1, 1}, 4, 4,
- {{0}, {8}, {0}, {0}},
- {{0}, {24}, {0}, {0}}},
-
- {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_P8, SVGA3DBLOCKDESC_NONE,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {8}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP,
- {1, 1, 1}, 4, 4,
- {{9}, {9}, {9}, {5}},
- {{18}, {9}, {0}, {27}}},
-
- {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE,
- {2, 1, 1}, 4, 4,
- {{0}, {8}, {8}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE,
- {2, 1, 1}, 4, 4,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{20}, {10}, {0}, {30}}},
-
- {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {24}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {8}, {24}, {0}},
- {{0}, {0}, {8}, {0}}},
-
- {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
- {2, 2, 1}, 6, 2,
- {{0}, {0}, {48}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
- {1, 1, 1}, 16, 16,
- {{32}, {32}, {32}, {32}},
- {{64}, {32}, {0}, {96}}},
-
- {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 8, 8,
- {{16}, {16}, {16}, {16}},
- {{32}, {16}, {0}, {48}}},
-
- {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
- {1, 1, 1}, 8, 8,
- {{0}, {32}, {32}, {0}},
- {{0}, {32}, {0}, {0}}},
-
- {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{10}, {10}, {10}, {2}},
- {{20}, {10}, {0}, {30}}},
-
- {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{16}, {8}, {0}, {24}}},
-
- {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
- {1, 1, 1}, 4, 4,
- {{0}, {16}, {16}, {0}},
- {{0}, {16}, {0}, {0}}},
-
- {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
- {1, 1, 1}, 4, 4,
- {{0}, {0}, {32}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {8}, {8}, {0}},
- {{0}, {8}, {0}, {0}}},
-
- {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM,
- {1, 1, 1}, 2, 2,
- {{0}, {0}, {16}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM,
- {1, 1, 1}, 1, 1,
- {{0}, {0}, {0}, {8}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
- {1, 1, 1}, 2, 2,
- {{5}, {6}, {5}, {0}},
- {{0}, {5}, {11}, {0}}},
-
- {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 2, 2,
- {{5}, {5}, {5}, {1}},
- {{0}, {5}, {10}, {15}}},
-
- {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {0}},
- {{0}, {8}, {16}, {24}}},
-
- {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
- {4, 4, 1}, 8, 8,
- {{0}, {0}, {64}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
- {1, 1, 1}, 2, 2,
- {{4}, {4}, {4}, {4}},
- {{0}, {4}, {8}, {12}}},
-
- {SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
- {4, 4, 1}, 16, 16,
- {{0}, {0}, {128}, {0}},
- {{0}, {0}, {0}, {0}}},
-
- {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
- {1, 1, 1}, 4, 4,
- {{8}, {8}, {8}, {8}},
- {{0}, {8}, {16}, {24}}},
-};
-
-static inline u32 clamped_umul32(u32 a, u32 b)
-{
- uint64_t tmp = (uint64_t) a*b;
- return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
-}
-
-/**
- * svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
- * given format.
- */
-static inline const struct svga3d_surface_desc *
-svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
-{
- if (format < ARRAY_SIZE(svga3d_surface_descs))
- return &svga3d_surface_descs[format];
-
- return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
-}
-
-/**
- * svga3dsurface_get_mip_size - Given a base level size and the mip level,
- * compute the size of the mip level.
- */
-static inline surf_size_struct
-svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
-{
- surf_size_struct size;
-
- size.width = max_t(u32, base_level.width >> mip_level, 1);
- size.height = max_t(u32, base_level.height >> mip_level, 1);
- size.depth = max_t(u32, base_level.depth >> mip_level, 1);
- size.pad64 = 0;
-
- return size;
-}
-
-static inline void
-svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
- const surf_size_struct *pixel_size,
- surf_size_struct *block_size)
-{
- block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
- desc->block_size.width);
- block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
- desc->block_size.height);
- block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
- desc->block_size.depth);
-}
-
-static inline bool
-svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
-{
- return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
-}
-
-static inline u32
-svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
- const surf_size_struct *size)
-{
- u32 pitch;
- surf_size_struct blocks;
-
- svga3dsurface_get_size_in_blocks(desc, size, &blocks);
-
- pitch = blocks.width * desc->pitch_bytes_per_block;
-
- return pitch;
-}
-
-/**
- * svga3dsurface_get_image_buffer_size - Calculates image buffer size.
- *
- * Return the number of bytes of buffer space required to store one image of a
- * surface, optionally using the specified pitch.
- *
- * If pitch is zero, it is assumed that rows are tightly packed.
- *
- * This function is overflow-safe. If the result would have overflowed, instead
- * we return MAX_UINT32.
- */
-static inline u32
-svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
- const surf_size_struct *size,
- u32 pitch)
-{
- surf_size_struct image_blocks;
- u32 slice_size, total_size;
-
- svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
-
- if (svga3dsurface_is_planar_surface(desc)) {
- total_size = clamped_umul32(image_blocks.width,
- image_blocks.height);
- total_size = clamped_umul32(total_size, image_blocks.depth);
- total_size = clamped_umul32(total_size, desc->bytes_per_block);
- return total_size;
- }
-
- if (pitch == 0)
- pitch = svga3dsurface_calculate_pitch(desc, size);
-
- slice_size = clamped_umul32(image_blocks.height, pitch);
- total_size = clamped_umul32(slice_size, image_blocks.depth);
-
- return total_size;
-}
-
-/**
- * svga3dsurface_get_serialized_size - Get the serialized size for the image.
- */
-static inline u32
-svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
- surf_size_struct base_level_size,
- u32 num_mip_levels,
- u32 num_layers)
-{
- const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
- u32 total_size = 0;
- u32 mip;
-
- for (mip = 0; mip < num_mip_levels; mip++) {
- surf_size_struct size =
- svga3dsurface_get_mip_size(base_level_size, mip);
- total_size += svga3dsurface_get_image_buffer_size(desc,
- &size, 0);
- }
-
- return total_size * num_layers;
-}
-
-/**
- * svga3dsurface_get_serialized_size_extended - Returns the number of bytes
- * required for a surface with given parameters. Support for sample count.
- */
-static inline u32
-svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
- surf_size_struct base_level_size,
- u32 num_mip_levels,
- u32 num_layers,
- u32 num_samples)
-{
- uint64_t total_size =
- svga3dsurface_get_serialized_size(format,
- base_level_size,
- num_mip_levels,
- num_layers);
- total_size *= max_t(u32, 1, num_samples);
-
- return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
-}
-
-/**
- * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
- * in an image (or volume).
- *
- * @width: The image width in pixels.
- * @height: The image height in pixels
- */
-static inline u32
-svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
- u32 width, u32 height,
- u32 x, u32 y, u32 z)
-{
- const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
- const u32 bw = desc->block_size.width, bh = desc->block_size.height;
- const u32 bd = desc->block_size.depth;
- const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
- desc->bytes_per_block;
- const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
- const u32 offset = (z / bd * imgstride +
- y / bh * rowstride +
- x / bw * desc->bytes_per_block);
- return offset;
-}
-
-static inline u32
-svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
- surf_size_struct baseLevelSize,
- u32 numMipLevels,
- u32 face,
- u32 mip)
-
-{
- u32 offset;
- u32 mipChainBytes;
- u32 mipChainBytesToLevel;
- u32 i;
- const struct svga3d_surface_desc *desc;
- surf_size_struct mipSize;
- u32 bytes;
-
- desc = svga3dsurface_get_desc(format);
-
- mipChainBytes = 0;
- mipChainBytesToLevel = 0;
- for (i = 0; i < numMipLevels; i++) {
- mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
- bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
- mipChainBytes += bytes;
- if (i < mip)
- mipChainBytesToLevel += bytes;
- }
-
- offset = mipChainBytes * face + mipChainBytesToLevel;
-
- return offset;
-}
-
-
-/**
- * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as
- * a ScreenTarget?
- * (with just the GBObjects cap-bit
- * set)
- * @format: format to queried
- *
- * RETURNS:
- * true if queried format is valid for screen targets
- */
-static inline bool
-svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
-{
- return (format == SVGA3D_X8R8G8B8 ||
- format == SVGA3D_A8R8G8B8 ||
- format == SVGA3D_R5G6B5 ||
- format == SVGA3D_X1R5G5B5 ||
- format == SVGA3D_A1R5G5B5 ||
- format == SVGA3D_P8);
-}
-
-
-/**
- * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as
- * a ScreenTarget?
- * (with DX10 enabled)
- *
- * @format: format to queried
- *
- * Results:
- * true if queried format is valid for screen targets
- */
-static inline bool
-svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
-{
- return (format == SVGA3D_R8G8B8A8_UNORM ||
- format == SVGA3D_B8G8R8A8_UNORM ||
- format == SVGA3D_B8G8R8X8_UNORM);
-}
-
-
-/**
- * svga3dsurface_is_screen_target_format - Is the specified format usable as a
- * ScreenTarget?
- * (for some combination of caps)
- *
- * @format: format to queried
- *
- * Results:
- * true if queried format is valid for screen targets
- */
-static inline bool
-svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
-{
- if (svga3dsurface_is_gb_screen_target_format(format)) {
- return true;
- }
- return svga3dsurface_is_dx_screen_target_format(format);
-}
-
-/**
- * struct svga3dsurface_mip - Mimpmap level information
- * @bytes: Bytes required in the backing store of this mipmap level.
- * @img_stride: Byte stride per image.
- * @row_stride: Byte stride per block row.
- * @size: The size of the mipmap.
- */
-struct svga3dsurface_mip {
- size_t bytes;
- size_t img_stride;
- size_t row_stride;
- struct drm_vmw_size size;
-
-};
-
-/**
- * struct svga3dsurface_cache - Cached surface information
- * @desc: Pointer to the surface descriptor
- * @mip: Array of mipmap level information. Valid size is @num_mip_levels.
- * @mip_chain_bytes: Bytes required in the backing store for the whole chain
- * of mip levels.
- * @sheet_bytes: Bytes required in the backing store for a sheet
- * representing a single sample.
- * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
- * a chain.
- * @num_layers: Number of slices in an array texture or number of faces in
- * a cubemap texture.
- */
-struct svga3dsurface_cache {
- const struct svga3d_surface_desc *desc;
- struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
- size_t mip_chain_bytes;
- size_t sheet_bytes;
- u32 num_mip_levels;
- u32 num_layers;
-};
-
-/**
- * struct svga3dsurface_loc - Surface location
- * @sheet: The multisample sheet.
- * @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
- * mip_level.
- * @x: X coordinate.
- * @y: Y coordinate.
- * @z: Z coordinate.
- */
-struct svga3dsurface_loc {
- u32 sheet;
- u32 sub_resource;
- u32 x, y, z;
+ SVGA3dBlockDesc blockDesc;
+
+ SVGA3dSize blockSize;
+ uint32 bytesPerBlock;
+ uint32 pitchBytesPerBlock;
+
+ SVGA3dChannelDef bitDepth;
+ SVGA3dChannelDef bitOffset;
+} SVGA3dSurfaceDesc;
+
+STATIC_CONST SVGA3dSurfaceDesc g_SVGA3dSurfaceDescs[] = {
+ { SVGA3D_FORMAT_INVALID,
+ SVGA3DBLOCKDESC_NONE,
+ { 1, 1, 1 },
+ 0,
+ 0,
+ { { 0 }, { 0 }, { 0 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_X8R8G8B8,
+ SVGA3DBLOCKDESC_RGB_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_A8R8G8B8,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_R5G6B5,
+ SVGA3DBLOCKDESC_RGB_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 5 }, { 6 }, { 5 }, { 0 } },
+ { { 0 }, { 5 }, { 11 }, { 0 } } },
+
+ { SVGA3D_X1R5G5B5,
+ SVGA3DBLOCKDESC_RGB_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 5 }, { 5 }, { 5 }, { 0 } },
+ { { 0 }, { 5 }, { 10 }, { 0 } } },
+
+ { SVGA3D_A1R5G5B5,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 5 }, { 5 }, { 5 }, { 1 } },
+ { { 0 }, { 5 }, { 10 }, { 15 } } },
+
+ { SVGA3D_A4R4G4B4,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 4 }, { 4 }, { 4 }, { 4 } },
+ { { 0 }, { 4 }, { 8 }, { 12 } } },
+
+ { SVGA3D_Z_D32,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_Z_D16,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_Z_D24S8,
+ SVGA3DBLOCKDESC_DS_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 24 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_Z_D15S1,
+ SVGA3DBLOCKDESC_DS_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 1 }, { 15 }, { 0 } },
+ { { 0 }, { 0 }, { 1 }, { 0 } } },
+
+ { SVGA3D_LUMINANCE8,
+ SVGA3DBLOCKDESC_L_UNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_LUMINANCE4_ALPHA4,
+ SVGA3DBLOCKDESC_LA_UNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 4 }, { 4 } },
+ { { 0 }, { 0 }, { 0 }, { 4 } } },
+
+ { SVGA3D_LUMINANCE16,
+ SVGA3DBLOCKDESC_L_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_LUMINANCE8_ALPHA8,
+ SVGA3DBLOCKDESC_LA_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 8 }, { 8 } },
+ { { 0 }, { 0 }, { 0 }, { 8 } } },
+
+ { SVGA3D_DXT1,
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_DXT2,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_DXT3,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_DXT4,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_DXT5,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BUMPU8V8,
+ SVGA3DBLOCKDESC_UV_SNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BUMPL6V5U5,
+ SVGA3DBLOCKDESC_UVL,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 6 }, { 5 }, { 5 }, { 0 } },
+ { { 10 }, { 5 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BUMPX8L8V8U8,
+ SVGA3DBLOCKDESC_UVL,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 16 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_FORMAT_DEAD1,
+ SVGA3DBLOCKDESC_NONE,
+ { 1, 1, 1 },
+ 3,
+ 3,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 16 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_ARGB_S10E5,
+ SVGA3DBLOCKDESC_RGBA_FP,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_ARGB_S23E8,
+ SVGA3DBLOCKDESC_RGBA_FP,
+ { 1, 1, 1 },
+ 16,
+ 16,
+ { { 32 }, { 32 }, { 32 }, { 32 } },
+ { { 64 }, { 32 }, { 0 }, { 96 } } },
+
+ { SVGA3D_A2R10G10B10,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 0 }, { 10 }, { 20 }, { 30 } } },
+
+ { SVGA3D_V8U8,
+ SVGA3DBLOCKDESC_UV_SNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_Q8W8V8U8,
+ SVGA3DBLOCKDESC_UVWQ_SNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_CxV8U8,
+ SVGA3DBLOCKDESC_UVCX_SNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_X8L8V8U8,
+ SVGA3DBLOCKDESC_UVL,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 16 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_A2W10V10U10,
+ SVGA3DBLOCKDESC_UVWA,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 20 }, { 10 }, { 0 }, { 30 } } },
+
+ { SVGA3D_ALPHA8,
+ SVGA3DBLOCKDESC_A_UNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 0 }, { 8 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R_S10E5,
+ SVGA3DBLOCKDESC_R_FP,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R_S23E8,
+ SVGA3DBLOCKDESC_R_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_RG_S10E5,
+ SVGA3DBLOCKDESC_RG_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_RG_S23E8,
+ SVGA3DBLOCKDESC_RG_FP,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 32 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BUFFER,
+ SVGA3DBLOCKDESC_BUFFER,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_Z_D24X8,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 24 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_V16U16,
+ SVGA3DBLOCKDESC_UV_SNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_G16R16,
+ SVGA3DBLOCKDESC_RG_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_A16B16G16R16,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_UYVY,
+ SVGA3DBLOCKDESC_YUV,
+ { 2, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_YUY2,
+ SVGA3DBLOCKDESC_YUV,
+ { 2, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 0 }, { 8 }, { 0 } },
+ { { 8 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_NV12,
+ SVGA3DBLOCKDESC_NV12,
+ { 2, 2, 1 },
+ 6,
+ 2,
+ { { 0 }, { 0 }, { 48 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_FORMAT_DEAD2,
+ SVGA3DBLOCKDESC_NONE,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_R32G32B32A32_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 16,
+ 16,
+ { { 32 }, { 32 }, { 32 }, { 32 } },
+ { { 64 }, { 32 }, { 0 }, { 96 } } },
+
+ { SVGA3D_R32G32B32A32_UINT,
+ SVGA3DBLOCKDESC_RGBA_UINT,
+ { 1, 1, 1 },
+ 16,
+ 16,
+ { { 32 }, { 32 }, { 32 }, { 32 } },
+ { { 64 }, { 32 }, { 0 }, { 96 } } },
+
+ { SVGA3D_R32G32B32A32_SINT,
+ SVGA3DBLOCKDESC_RGBA_SINT,
+ { 1, 1, 1 },
+ 16,
+ 16,
+ { { 32 }, { 32 }, { 32 }, { 32 } },
+ { { 64 }, { 32 }, { 0 }, { 96 } } },
+
+ { SVGA3D_R32G32B32_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 12,
+ 12,
+ { { 32 }, { 32 }, { 32 }, { 0 } },
+ { { 64 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32B32_FLOAT,
+ SVGA3DBLOCKDESC_RGB_FP,
+ { 1, 1, 1 },
+ 12,
+ 12,
+ { { 32 }, { 32 }, { 32 }, { 0 } },
+ { { 64 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32B32_UINT,
+ SVGA3DBLOCKDESC_RGB_UINT,
+ { 1, 1, 1 },
+ 12,
+ 12,
+ { { 32 }, { 32 }, { 32 }, { 0 } },
+ { { 64 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32B32_SINT,
+ SVGA3DBLOCKDESC_RGB_SINT,
+ { 1, 1, 1 },
+ 12,
+ 12,
+ { { 32 }, { 32 }, { 32 }, { 0 } },
+ { { 64 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16G16B16A16_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R16G16B16A16_UINT,
+ SVGA3DBLOCKDESC_RGBA_UINT,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R16G16B16A16_SNORM,
+ SVGA3DBLOCKDESC_RGBA_SNORM,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R16G16B16A16_SINT,
+ SVGA3DBLOCKDESC_RGBA_SINT,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R32G32_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 32 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32_UINT,
+ SVGA3DBLOCKDESC_RG_UINT,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 32 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32_SINT,
+ SVGA3DBLOCKDESC_RG_SINT,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 32 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G8X24_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 8 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_D32_FLOAT_S8X24_UINT,
+ SVGA3DBLOCKDESC_DS,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 8 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32_FLOAT_X8X24,
+ SVGA3DBLOCKDESC_R_FP,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_X32_G8X24_UINT,
+ SVGA3DBLOCKDESC_G_UINT,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 8 }, { 0 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R10G10B10A2_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 20 }, { 10 }, { 0 }, { 30 } } },
+
+ { SVGA3D_R10G10B10A2_UINT,
+ SVGA3DBLOCKDESC_RGBA_UINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 20 }, { 10 }, { 0 }, { 30 } } },
+
+ { SVGA3D_R11G11B10_FLOAT,
+ SVGA3DBLOCKDESC_RGB_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 11 }, { 11 }, { 0 } },
+ { { 22 }, { 11 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8B8A8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R8G8B8A8_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R8G8B8A8_UNORM_SRGB,
+ SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R8G8B8A8_UINT,
+ SVGA3DBLOCKDESC_RGBA_UINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R8G8B8A8_SINT,
+ SVGA3DBLOCKDESC_RGBA_SINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R16G16_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16G16_UINT,
+ SVGA3DBLOCKDESC_RG_UINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16G16_SINT,
+ SVGA3DBLOCKDESC_RG_SINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_D32_FLOAT,
+ SVGA3DBLOCKDESC_DEPTH_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32_UINT,
+ SVGA3DBLOCKDESC_R_UINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32_SINT,
+ SVGA3DBLOCKDESC_R_SINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R24G8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 24 }, { 0 } },
+ { { 0 }, { 24 }, { 0 }, { 0 } } },
+
+ { SVGA3D_D24_UNORM_S8_UINT,
+ SVGA3DBLOCKDESC_DS_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 24 }, { 0 } },
+ { { 0 }, { 24 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R24_UNORM_X8,
+ SVGA3DBLOCKDESC_R_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 24 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_X24_G8_UINT,
+ SVGA3DBLOCKDESC_G_UINT,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 0 }, { 0 } },
+ { { 0 }, { 24 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8_UNORM,
+ SVGA3DBLOCKDESC_RG_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8_UINT,
+ SVGA3DBLOCKDESC_RG_UINT,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8_SINT,
+ SVGA3DBLOCKDESC_RG_SINT,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_UNORM,
+ SVGA3DBLOCKDESC_R_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_UINT,
+ SVGA3DBLOCKDESC_R_UINT,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_SNORM,
+ SVGA3DBLOCKDESC_R_SNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_SINT,
+ SVGA3DBLOCKDESC_R_SINT,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8_UNORM,
+ SVGA3DBLOCKDESC_R_UNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8_UINT,
+ SVGA3DBLOCKDESC_R_UINT,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8_SNORM,
+ SVGA3DBLOCKDESC_R_SNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8_SINT,
+ SVGA3DBLOCKDESC_R_SINT,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_P8,
+ SVGA3DBLOCKDESC_NONE,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R9G9B9E5_SHAREDEXP,
+ SVGA3DBLOCKDESC_RGB_EXP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 9 }, { 9 }, { 9 }, { 5 } },
+ { { 18 }, { 9 }, { 0 }, { 27 } } },
+
+ { SVGA3D_R8G8_B8G8_UNORM,
+ SVGA3DBLOCKDESC_NONE,
+ { 2, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_G8R8_G8B8_UNORM,
+ SVGA3DBLOCKDESC_NONE,
+ { 2, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC1_TYPELESS,
+ SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC1_UNORM_SRGB,
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC2_TYPELESS,
+ SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC2_UNORM_SRGB,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC3_TYPELESS,
+ SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC3_UNORM_SRGB,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC4_TYPELESS,
+ SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_ATI1,
+ SVGA3DBLOCKDESC_BC4_COMP_UNORM,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC4_SNORM,
+ SVGA3DBLOCKDESC_BC4_COMP_SNORM,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC5_TYPELESS,
+ SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_ATI2,
+ SVGA3DBLOCKDESC_BC5_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC5_SNORM,
+ SVGA3DBLOCKDESC_BC5_COMP_SNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R10G10B10_XR_BIAS_A2_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 20 }, { 10 }, { 0 }, { 30 } } },
+
+ { SVGA3D_B8G8R8A8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_B8G8R8A8_UNORM_SRGB,
+ SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_B8G8R8X8_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_B8G8R8X8_UNORM_SRGB,
+ SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_Z_DF16,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_Z_DF24,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 24 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_Z_D24S8_INT,
+ SVGA3DBLOCKDESC_DS_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 8 }, { 24 }, { 0 } },
+ { { 0 }, { 0 }, { 8 }, { 0 } } },
+
+ { SVGA3D_YV12,
+ SVGA3DBLOCKDESC_YV12,
+ { 2, 2, 1 },
+ 6,
+ 2,
+ { { 0 }, { 0 }, { 48 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32G32B32A32_FLOAT,
+ SVGA3DBLOCKDESC_RGBA_FP,
+ { 1, 1, 1 },
+ 16,
+ 16,
+ { { 32 }, { 32 }, { 32 }, { 32 } },
+ { { 64 }, { 32 }, { 0 }, { 96 } } },
+
+ { SVGA3D_R16G16B16A16_FLOAT,
+ SVGA3DBLOCKDESC_RGBA_FP,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R16G16B16A16_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 16 }, { 16 }, { 16 }, { 16 } },
+ { { 32 }, { 16 }, { 0 }, { 48 } } },
+
+ { SVGA3D_R32G32_FLOAT,
+ SVGA3DBLOCKDESC_RG_FP,
+ { 1, 1, 1 },
+ 8,
+ 8,
+ { { 0 }, { 32 }, { 32 }, { 0 } },
+ { { 0 }, { 32 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R10G10B10A2_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 10 }, { 10 }, { 2 } },
+ { { 20 }, { 10 }, { 0 }, { 30 } } },
+
+ { SVGA3D_R8G8B8A8_SNORM,
+ SVGA3DBLOCKDESC_RGBA_SNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 16 }, { 8 }, { 0 }, { 24 } } },
+
+ { SVGA3D_R16G16_FLOAT,
+ SVGA3DBLOCKDESC_RG_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16G16_UNORM,
+ SVGA3DBLOCKDESC_RG_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16G16_SNORM,
+ SVGA3DBLOCKDESC_RG_SNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 16 }, { 16 }, { 0 } },
+ { { 0 }, { 16 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R32_FLOAT,
+ SVGA3DBLOCKDESC_R_FP,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 0 }, { 0 }, { 32 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R8G8_SNORM,
+ SVGA3DBLOCKDESC_RG_SNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 0 }, { 0 } } },
+
+ { SVGA3D_R16_FLOAT,
+ SVGA3DBLOCKDESC_R_FP,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_D16_UNORM,
+ SVGA3DBLOCKDESC_DEPTH_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 0 }, { 0 }, { 16 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_A8_UNORM,
+ SVGA3DBLOCKDESC_A_UNORM,
+ { 1, 1, 1 },
+ 1,
+ 1,
+ { { 0 }, { 0 }, { 0 }, { 8 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC1_UNORM,
+ SVGA3DBLOCKDESC_BC1_COMP_UNORM,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC2_UNORM,
+ SVGA3DBLOCKDESC_BC2_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC3_UNORM,
+ SVGA3DBLOCKDESC_BC3_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_B5G6R5_UNORM,
+ SVGA3DBLOCKDESC_RGB_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 5 }, { 6 }, { 5 }, { 0 } },
+ { { 0 }, { 5 }, { 11 }, { 0 } } },
+
+ { SVGA3D_B5G5R5A1_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 5 }, { 5 }, { 5 }, { 1 } },
+ { { 0 }, { 5 }, { 10 }, { 15 } } },
+
+ { SVGA3D_B8G8R8A8_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_B8G8R8X8_UNORM,
+ SVGA3DBLOCKDESC_RGB_UNORM,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 0 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_BC4_UNORM,
+ SVGA3DBLOCKDESC_BC4_COMP_UNORM,
+ { 4, 4, 1 },
+ 8,
+ 8,
+ { { 0 }, { 0 }, { 64 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC5_UNORM,
+ SVGA3DBLOCKDESC_BC5_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_B4G4R4A4_UNORM,
+ SVGA3DBLOCKDESC_RGBA_UNORM,
+ { 1, 1, 1 },
+ 2,
+ 2,
+ { { 4 }, { 4 }, { 4 }, { 4 } },
+ { { 0 }, { 4 }, { 8 }, { 12 } } },
+
+ { SVGA3D_BC6H_TYPELESS,
+ SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC6H_UF16,
+ SVGA3DBLOCKDESC_BC6H_COMP_UF16,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC6H_SF16,
+ SVGA3DBLOCKDESC_BC6H_COMP_SF16,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC7_TYPELESS,
+ SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC7_UNORM,
+ SVGA3DBLOCKDESC_BC7_COMP_UNORM,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_BC7_UNORM_SRGB,
+ SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
+ { 4, 4, 1 },
+ 16,
+ 16,
+ { { 0 }, { 0 }, { 128 }, { 0 } },
+ { { 0 }, { 0 }, { 0 }, { 0 } } },
+
+ { SVGA3D_AYUV,
+ SVGA3DBLOCKDESC_AYUV,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 8 }, { 8 }, { 8 }, { 8 } },
+ { { 0 }, { 8 }, { 16 }, { 24 } } },
+
+ { SVGA3D_R11G11B10_TYPELESS,
+ SVGA3DBLOCKDESC_TYPELESS,
+ { 1, 1, 1 },
+ 4,
+ 4,
+ { { 10 }, { 11 }, { 11 }, { 0 } },
+ { { 22 }, { 11 }, { 0 }, { 0 } } },
};
-/**
- * svga3dsurface_subres - Compute the subresource from layer and mipmap.
- * @cache: Surface layout data.
- * @mip_level: The mipmap level.
- * @layer: The surface layer (face or array slice).
- *
- * Return: The subresource.
- */
-static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache,
- u32 mip_level, u32 layer)
-{
- return cache->num_mip_levels * layer + mip_level;
-}
-
-/**
- * svga3dsurface_setup_cache - Build a surface cache entry
- * @size: The surface base level dimensions.
- * @format: The surface format.
- * @num_mip_levels: Number of mipmap levels.
- * @num_layers: Number of layers.
- * @cache: Pointer to a struct svga3dsurface_cach object to be filled in.
- *
- * Return: Zero on success, -EINVAL on invalid surface layout.
- */
-static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size,
- SVGA3dSurfaceFormat format,
- u32 num_mip_levels,
- u32 num_layers,
- u32 num_samples,
- struct svga3dsurface_cache *cache)
-{
- const struct svga3d_surface_desc *desc;
- u32 i;
-
- memset(cache, 0, sizeof(*cache));
- cache->desc = desc = svga3dsurface_get_desc(format);
- cache->num_mip_levels = num_mip_levels;
- cache->num_layers = num_layers;
- for (i = 0; i < cache->num_mip_levels; i++) {
- struct svga3dsurface_mip *mip = &cache->mip[i];
-
- mip->size = svga3dsurface_get_mip_size(*size, i);
- mip->bytes = svga3dsurface_get_image_buffer_size
- (desc, &mip->size, 0);
- mip->row_stride =
- __KERNEL_DIV_ROUND_UP(mip->size.width,
- desc->block_size.width) *
- desc->bytes_per_block * num_samples;
- if (!mip->row_stride)
- goto invalid_dim;
-
- mip->img_stride =
- __KERNEL_DIV_ROUND_UP(mip->size.height,
- desc->block_size.height) *
- mip->row_stride;
- if (!mip->img_stride)
- goto invalid_dim;
-
- cache->mip_chain_bytes += mip->bytes;
- }
- cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
- if (!cache->sheet_bytes)
- goto invalid_dim;
-
- return 0;
-
-invalid_dim:
- VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
- return -EINVAL;
-}
-
-/**
- * svga3dsurface_get_loc - Get a surface location from an offset into the
- * backing store
- * @cache: Surface layout data.
- * @loc: Pointer to a struct svga3dsurface_loc to be filled in.
- * @offset: Offset into the surface backing store.
- */
-static inline void
-svga3dsurface_get_loc(const struct svga3dsurface_cache *cache,
- struct svga3dsurface_loc *loc,
- size_t offset)
-{
- const struct svga3dsurface_mip *mip = &cache->mip[0];
- const struct svga3d_surface_desc *desc = cache->desc;
- u32 layer;
- int i;
-
- loc->sheet = offset / cache->sheet_bytes;
- offset -= loc->sheet * cache->sheet_bytes;
-
- layer = offset / cache->mip_chain_bytes;
- offset -= layer * cache->mip_chain_bytes;
- for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
- if (mip->bytes > offset)
- break;
- offset -= mip->bytes;
- }
-
- loc->sub_resource = svga3dsurface_subres(cache, i, layer);
- loc->z = offset / mip->img_stride;
- offset -= loc->z * mip->img_stride;
- loc->z *= desc->block_size.depth;
- loc->y = offset / mip->row_stride;
- offset -= loc->y * mip->row_stride;
- loc->y *= desc->block_size.height;
- loc->x = offset / desc->bytes_per_block;
- loc->x *= desc->block_size.width;
-}
-
-/**
- * svga3dsurface_inc_loc - Clamp increment a surface location with one block
- * size
- * in each dimension.
- * @loc: Pointer to a struct svga3dsurface_loc to be incremented.
- *
- * When computing the size of a range as size = end - start, the range does not
- * include the end element. However a location representing the last byte
- * of a touched region in the backing store *is* included in the range.
- * This function modifies such a location to match the end definition
- * given as start + size which is the one used in a SVGA3dBox.
- */
-static inline void
-svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache,
- struct svga3dsurface_loc *loc)
-{
- const struct svga3d_surface_desc *desc = cache->desc;
- u32 mip = loc->sub_resource % cache->num_mip_levels;
- const struct drm_vmw_size *size = &cache->mip[mip].size;
-
- loc->sub_resource++;
- loc->x += desc->block_size.width;
- if (loc->x > size->width)
- loc->x = size->width;
- loc->y += desc->block_size.height;
- if (loc->y > size->height)
- loc->y = size->height;
- loc->z += desc->block_size.depth;
- if (loc->z > size->depth)
- loc->z = size->depth;
-}
-
-/**
- * svga3dsurface_min_loc - The start location in a subresource
- * @cache: Surface layout data.
- * @sub_resource: The subresource.
- * @loc: Pointer to a struct svga3dsurface_loc to be filled in.
- */
-static inline void
-svga3dsurface_min_loc(const struct svga3dsurface_cache *cache,
- u32 sub_resource,
- struct svga3dsurface_loc *loc)
-{
- loc->sheet = 0;
- loc->sub_resource = sub_resource;
- loc->x = loc->y = loc->z = 0;
-}
-
-/**
- * svga3dsurface_min_loc - The end location in a subresource
- * @cache: Surface layout data.
- * @sub_resource: The subresource.
- * @loc: Pointer to a struct svga3dsurface_loc to be filled in.
- *
- * Following the end definition given in svga3dsurface_inc_loc(),
- * Compute the end location of a surface subresource.
- */
-static inline void
-svga3dsurface_max_loc(const struct svga3dsurface_cache *cache,
- u32 sub_resource,
- struct svga3dsurface_loc *loc)
-{
- const struct drm_vmw_size *size;
- u32 mip;
-
- loc->sheet = 0;
- loc->sub_resource = sub_resource + 1;
- mip = sub_resource % cache->num_mip_levels;
- size = &cache->mip[mip].size;
- loc->x = size->width;
- loc->y = size->height;
- loc->z = size->depth;
+#ifdef __cplusplus
}
+#endif
-#endif /* _SVGA3D_SURFACEDEFS_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
index 77e338a65791f3d4b0e503d995440d6fcfb1d695..70b88ee16cf6e486aaf3cf78e1b5091220998f5f 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2012-2015 VMware, Inc.
+ * Copyright 2012-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -27,1974 +27,1530 @@
/*
* svga3d_types.h --
*
- * SVGA 3d hardware definitions for basic types
+ * SVGA 3d hardware definitions for basic types
*/
+
+
#ifndef _SVGA3D_TYPES_H_
#define _SVGA3D_TYPES_H_
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-
-#include "includeCheck.h"
+#include "vm_basic_types.h"
-/*
- * Generic Types
- */
+#define SVGA3D_INVALID_ID ((uint32)-1)
-#define SVGA3D_INVALID_ID ((uint32)-1)
+#define SVGA3D_RESOURCE_TYPE_MIN 1
+#define SVGA3D_RESOURCE_BUFFER 1
+#define SVGA3D_RESOURCE_TEXTURE1D 2
+#define SVGA3D_RESOURCE_TEXTURE2D 3
+#define SVGA3D_RESOURCE_TEXTURE3D 4
+#define SVGA3D_RESOURCE_TEXTURECUBE 5
+#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
+#define SVGA3D_RESOURCE_BUFFEREX 6
+#define SVGA3D_RESOURCE_TYPE_MAX 7
+typedef uint32 SVGA3dResourceType;
-typedef uint8 SVGABool8; /* 8-bit Bool definition */
-typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
-typedef uint32 SVGA3dColor; /* a, r, g, b */
+typedef uint8 SVGABool8;
+typedef uint32 SVGA3dBool;
+typedef uint32 SVGA3dColor;
typedef uint32 SVGA3dSurfaceId;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 numerator;
- uint32 denominator;
-}
-#include "vmware_pack_end.h"
-SVGA3dFraction64;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCopyRect {
- uint32 x;
- uint32 y;
- uint32 w;
- uint32 h;
- uint32 srcx;
- uint32 srcy;
-}
-#include "vmware_pack_end.h"
-SVGA3dCopyRect;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dCopyBox {
- uint32 x;
- uint32 y;
- uint32 z;
- uint32 w;
- uint32 h;
- uint32 d;
- uint32 srcx;
- uint32 srcy;
- uint32 srcz;
-}
-#include "vmware_pack_end.h"
-SVGA3dCopyBox;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dRect {
- uint32 x;
- uint32 y;
- uint32 w;
- uint32 h;
-}
-#include "vmware_pack_end.h"
-SVGA3dRect;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 x;
- uint32 y;
- uint32 z;
- uint32 w;
- uint32 h;
- uint32 d;
-}
-#include "vmware_pack_end.h"
-SVGA3dBox;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- int32 x;
- int32 y;
- int32 z;
- int32 w;
- int32 h;
- int32 d;
-}
-#include "vmware_pack_end.h"
-SVGA3dSignedBox;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 x;
- uint32 y;
- uint32 z;
-}
-#include "vmware_pack_end.h"
-SVGA3dPoint;
+#pragma pack(push, 1)
+typedef struct {
+ uint32 numerator;
+ uint32 denominator;
+} SVGA3dFraction64;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCopyRect {
+ uint32 x;
+ uint32 y;
+ uint32 w;
+ uint32 h;
+ uint32 srcx;
+ uint32 srcy;
+} SVGA3dCopyRect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dCopyBox {
+ uint32 x;
+ uint32 y;
+ uint32 z;
+ uint32 w;
+ uint32 h;
+ uint32 d;
+ uint32 srcx;
+ uint32 srcy;
+ uint32 srcz;
+} SVGA3dCopyBox;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dRect {
+ uint32 x;
+ uint32 y;
+ uint32 w;
+ uint32 h;
+} SVGA3dRect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 x;
+ uint32 y;
+ uint32 z;
+ uint32 w;
+ uint32 h;
+ uint32 d;
+} SVGA3dBox;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ int32 x;
+ int32 y;
+ int32 z;
+ int32 w;
+ int32 h;
+ int32 d;
+} SVGA3dSignedBox;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 x;
+ uint32 y;
+ uint32 z;
+} SVGA3dPoint;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef union {
+ struct {
+ float r;
+ float g;
+ float b;
+ float a;
+ };
+
+ float value[4];
+} SVGA3dRGBAFloat;
+#pragma pack(pop)
-/*
- * Surface formats.
- */
typedef enum SVGA3dSurfaceFormat {
- SVGA3D_FORMAT_INVALID = 0,
-
- SVGA3D_X8R8G8B8 = 1,
- SVGA3D_FORMAT_MIN = 1,
-
- SVGA3D_A8R8G8B8 = 2,
-
- SVGA3D_R5G6B5 = 3,
- SVGA3D_X1R5G5B5 = 4,
- SVGA3D_A1R5G5B5 = 5,
- SVGA3D_A4R4G4B4 = 6,
-
- SVGA3D_Z_D32 = 7,
- SVGA3D_Z_D16 = 8,
- SVGA3D_Z_D24S8 = 9,
- SVGA3D_Z_D15S1 = 10,
-
- SVGA3D_LUMINANCE8 = 11,
- SVGA3D_LUMINANCE4_ALPHA4 = 12,
- SVGA3D_LUMINANCE16 = 13,
- SVGA3D_LUMINANCE8_ALPHA8 = 14,
-
- SVGA3D_DXT1 = 15,
- SVGA3D_DXT2 = 16,
- SVGA3D_DXT3 = 17,
- SVGA3D_DXT4 = 18,
- SVGA3D_DXT5 = 19,
-
- SVGA3D_BUMPU8V8 = 20,
- SVGA3D_BUMPL6V5U5 = 21,
- SVGA3D_BUMPX8L8V8U8 = 22,
- SVGA3D_FORMAT_DEAD1 = 23,
-
- SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
- SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
-
- SVGA3D_A2R10G10B10 = 26,
-
- /* signed formats */
- SVGA3D_V8U8 = 27,
- SVGA3D_Q8W8V8U8 = 28,
- SVGA3D_CxV8U8 = 29,
-
- /* mixed formats */
- SVGA3D_X8L8V8U8 = 30,
- SVGA3D_A2W10V10U10 = 31,
-
- SVGA3D_ALPHA8 = 32,
-
- /* Single- and dual-component floating point formats */
- SVGA3D_R_S10E5 = 33,
- SVGA3D_R_S23E8 = 34,
- SVGA3D_RG_S10E5 = 35,
- SVGA3D_RG_S23E8 = 36,
-
- SVGA3D_BUFFER = 37,
-
- SVGA3D_Z_D24X8 = 38,
-
- SVGA3D_V16U16 = 39,
-
- SVGA3D_G16R16 = 40,
- SVGA3D_A16B16G16R16 = 41,
-
- /* Packed Video formats */
- SVGA3D_UYVY = 42,
- SVGA3D_YUY2 = 43,
-
- /* Planar video formats */
- SVGA3D_NV12 = 44,
-
- SVGA3D_FORMAT_DEAD2 = 45,
-
- SVGA3D_R32G32B32A32_TYPELESS = 46,
- SVGA3D_R32G32B32A32_UINT = 47,
- SVGA3D_R32G32B32A32_SINT = 48,
- SVGA3D_R32G32B32_TYPELESS = 49,
- SVGA3D_R32G32B32_FLOAT = 50,
- SVGA3D_R32G32B32_UINT = 51,
- SVGA3D_R32G32B32_SINT = 52,
- SVGA3D_R16G16B16A16_TYPELESS = 53,
- SVGA3D_R16G16B16A16_UINT = 54,
- SVGA3D_R16G16B16A16_SNORM = 55,
- SVGA3D_R16G16B16A16_SINT = 56,
- SVGA3D_R32G32_TYPELESS = 57,
- SVGA3D_R32G32_UINT = 58,
- SVGA3D_R32G32_SINT = 59,
- SVGA3D_R32G8X24_TYPELESS = 60,
- SVGA3D_D32_FLOAT_S8X24_UINT = 61,
- SVGA3D_R32_FLOAT_X8X24 = 62,
- SVGA3D_X32_G8X24_UINT = 63,
- SVGA3D_R10G10B10A2_TYPELESS = 64,
- SVGA3D_R10G10B10A2_UINT = 65,
- SVGA3D_R11G11B10_FLOAT = 66,
- SVGA3D_R8G8B8A8_TYPELESS = 67,
- SVGA3D_R8G8B8A8_UNORM = 68,
- SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
- SVGA3D_R8G8B8A8_UINT = 70,
- SVGA3D_R8G8B8A8_SINT = 71,
- SVGA3D_R16G16_TYPELESS = 72,
- SVGA3D_R16G16_UINT = 73,
- SVGA3D_R16G16_SINT = 74,
- SVGA3D_R32_TYPELESS = 75,
- SVGA3D_D32_FLOAT = 76,
- SVGA3D_R32_UINT = 77,
- SVGA3D_R32_SINT = 78,
- SVGA3D_R24G8_TYPELESS = 79,
- SVGA3D_D24_UNORM_S8_UINT = 80,
- SVGA3D_R24_UNORM_X8 = 81,
- SVGA3D_X24_G8_UINT = 82,
- SVGA3D_R8G8_TYPELESS = 83,
- SVGA3D_R8G8_UNORM = 84,
- SVGA3D_R8G8_UINT = 85,
- SVGA3D_R8G8_SINT = 86,
- SVGA3D_R16_TYPELESS = 87,
- SVGA3D_R16_UNORM = 88,
- SVGA3D_R16_UINT = 89,
- SVGA3D_R16_SNORM = 90,
- SVGA3D_R16_SINT = 91,
- SVGA3D_R8_TYPELESS = 92,
- SVGA3D_R8_UNORM = 93,
- SVGA3D_R8_UINT = 94,
- SVGA3D_R8_SNORM = 95,
- SVGA3D_R8_SINT = 96,
- SVGA3D_P8 = 97,
- SVGA3D_R9G9B9E5_SHAREDEXP = 98,
- SVGA3D_R8G8_B8G8_UNORM = 99,
- SVGA3D_G8R8_G8B8_UNORM = 100,
- SVGA3D_BC1_TYPELESS = 101,
- SVGA3D_BC1_UNORM_SRGB = 102,
- SVGA3D_BC2_TYPELESS = 103,
- SVGA3D_BC2_UNORM_SRGB = 104,
- SVGA3D_BC3_TYPELESS = 105,
- SVGA3D_BC3_UNORM_SRGB = 106,
- SVGA3D_BC4_TYPELESS = 107,
- SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */
- SVGA3D_BC4_SNORM = 109,
- SVGA3D_BC5_TYPELESS = 110,
- SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */
- SVGA3D_BC5_SNORM = 112,
- SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
- SVGA3D_B8G8R8A8_TYPELESS = 114,
- SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
- SVGA3D_B8G8R8X8_TYPELESS = 116,
- SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
-
- /* Advanced depth formats. */
- SVGA3D_Z_DF16 = 118,
- SVGA3D_Z_DF24 = 119,
- SVGA3D_Z_D24S8_INT = 120,
-
- /* Planar video formats. */
- SVGA3D_YV12 = 121,
-
- SVGA3D_R32G32B32A32_FLOAT = 122,
- SVGA3D_R16G16B16A16_FLOAT = 123,
- SVGA3D_R16G16B16A16_UNORM = 124,
- SVGA3D_R32G32_FLOAT = 125,
- SVGA3D_R10G10B10A2_UNORM = 126,
- SVGA3D_R8G8B8A8_SNORM = 127,
- SVGA3D_R16G16_FLOAT = 128,
- SVGA3D_R16G16_UNORM = 129,
- SVGA3D_R16G16_SNORM = 130,
- SVGA3D_R32_FLOAT = 131,
- SVGA3D_R8G8_SNORM = 132,
- SVGA3D_R16_FLOAT = 133,
- SVGA3D_D16_UNORM = 134,
- SVGA3D_A8_UNORM = 135,
- SVGA3D_BC1_UNORM = 136,
- SVGA3D_BC2_UNORM = 137,
- SVGA3D_BC3_UNORM = 138,
- SVGA3D_B5G6R5_UNORM = 139,
- SVGA3D_B5G5R5A1_UNORM = 140,
- SVGA3D_B8G8R8A8_UNORM = 141,
- SVGA3D_B8G8R8X8_UNORM = 142,
- SVGA3D_BC4_UNORM = 143,
- SVGA3D_BC5_UNORM = 144,
- SVGA3D_B4G4R4A4_UNORM = 145,
-
- /* DX11 compressed formats */
- SVGA3D_BC6H_TYPELESS = 146,
- SVGA3D_BC6H_UF16 = 147,
- SVGA3D_BC6H_SF16 = 148,
- SVGA3D_BC7_TYPELESS = 149,
- SVGA3D_BC7_UNORM = 150,
- SVGA3D_BC7_UNORM_SRGB = 151,
-
- /* Video format with alpha */
- SVGA3D_AYUV = 152,
-
- SVGA3D_FORMAT_MAX
+ SVGA3D_FORMAT_INVALID = 0,
+
+ SVGA3D_X8R8G8B8 = 1,
+ SVGA3D_FORMAT_MIN = 1,
+
+ SVGA3D_A8R8G8B8 = 2,
+
+ SVGA3D_R5G6B5 = 3,
+ SVGA3D_X1R5G5B5 = 4,
+ SVGA3D_A1R5G5B5 = 5,
+ SVGA3D_A4R4G4B4 = 6,
+
+ SVGA3D_Z_D32 = 7,
+ SVGA3D_Z_D16 = 8,
+ SVGA3D_Z_D24S8 = 9,
+ SVGA3D_Z_D15S1 = 10,
+
+ SVGA3D_LUMINANCE8 = 11,
+ SVGA3D_LUMINANCE4_ALPHA4 = 12,
+ SVGA3D_LUMINANCE16 = 13,
+ SVGA3D_LUMINANCE8_ALPHA8 = 14,
+
+ SVGA3D_DXT1 = 15,
+ SVGA3D_DXT2 = 16,
+ SVGA3D_DXT3 = 17,
+ SVGA3D_DXT4 = 18,
+ SVGA3D_DXT5 = 19,
+
+ SVGA3D_BUMPU8V8 = 20,
+ SVGA3D_BUMPL6V5U5 = 21,
+ SVGA3D_BUMPX8L8V8U8 = 22,
+ SVGA3D_FORMAT_DEAD1 = 23,
+
+ SVGA3D_ARGB_S10E5 = 24,
+ SVGA3D_ARGB_S23E8 = 25,
+
+ SVGA3D_A2R10G10B10 = 26,
+
+ SVGA3D_V8U8 = 27,
+ SVGA3D_Q8W8V8U8 = 28,
+ SVGA3D_CxV8U8 = 29,
+
+ SVGA3D_X8L8V8U8 = 30,
+ SVGA3D_A2W10V10U10 = 31,
+
+ SVGA3D_ALPHA8 = 32,
+
+ SVGA3D_R_S10E5 = 33,
+ SVGA3D_R_S23E8 = 34,
+ SVGA3D_RG_S10E5 = 35,
+ SVGA3D_RG_S23E8 = 36,
+
+ SVGA3D_BUFFER = 37,
+
+ SVGA3D_Z_D24X8 = 38,
+
+ SVGA3D_V16U16 = 39,
+
+ SVGA3D_G16R16 = 40,
+ SVGA3D_A16B16G16R16 = 41,
+
+ SVGA3D_UYVY = 42,
+ SVGA3D_YUY2 = 43,
+
+ SVGA3D_NV12 = 44,
+
+ SVGA3D_FORMAT_DEAD2 = 45,
+
+ SVGA3D_R32G32B32A32_TYPELESS = 46,
+ SVGA3D_R32G32B32A32_UINT = 47,
+ SVGA3D_R32G32B32A32_SINT = 48,
+ SVGA3D_R32G32B32_TYPELESS = 49,
+ SVGA3D_R32G32B32_FLOAT = 50,
+ SVGA3D_R32G32B32_UINT = 51,
+ SVGA3D_R32G32B32_SINT = 52,
+ SVGA3D_R16G16B16A16_TYPELESS = 53,
+ SVGA3D_R16G16B16A16_UINT = 54,
+ SVGA3D_R16G16B16A16_SNORM = 55,
+ SVGA3D_R16G16B16A16_SINT = 56,
+ SVGA3D_R32G32_TYPELESS = 57,
+ SVGA3D_R32G32_UINT = 58,
+ SVGA3D_R32G32_SINT = 59,
+ SVGA3D_R32G8X24_TYPELESS = 60,
+ SVGA3D_D32_FLOAT_S8X24_UINT = 61,
+ SVGA3D_R32_FLOAT_X8X24 = 62,
+ SVGA3D_X32_G8X24_UINT = 63,
+ SVGA3D_R10G10B10A2_TYPELESS = 64,
+ SVGA3D_R10G10B10A2_UINT = 65,
+ SVGA3D_R11G11B10_FLOAT = 66,
+ SVGA3D_R8G8B8A8_TYPELESS = 67,
+ SVGA3D_R8G8B8A8_UNORM = 68,
+ SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
+ SVGA3D_R8G8B8A8_UINT = 70,
+ SVGA3D_R8G8B8A8_SINT = 71,
+ SVGA3D_R16G16_TYPELESS = 72,
+ SVGA3D_R16G16_UINT = 73,
+ SVGA3D_R16G16_SINT = 74,
+ SVGA3D_R32_TYPELESS = 75,
+ SVGA3D_D32_FLOAT = 76,
+ SVGA3D_R32_UINT = 77,
+ SVGA3D_R32_SINT = 78,
+ SVGA3D_R24G8_TYPELESS = 79,
+ SVGA3D_D24_UNORM_S8_UINT = 80,
+ SVGA3D_R24_UNORM_X8 = 81,
+ SVGA3D_X24_G8_UINT = 82,
+ SVGA3D_R8G8_TYPELESS = 83,
+ SVGA3D_R8G8_UNORM = 84,
+ SVGA3D_R8G8_UINT = 85,
+ SVGA3D_R8G8_SINT = 86,
+ SVGA3D_R16_TYPELESS = 87,
+ SVGA3D_R16_UNORM = 88,
+ SVGA3D_R16_UINT = 89,
+ SVGA3D_R16_SNORM = 90,
+ SVGA3D_R16_SINT = 91,
+ SVGA3D_R8_TYPELESS = 92,
+ SVGA3D_R8_UNORM = 93,
+ SVGA3D_R8_UINT = 94,
+ SVGA3D_R8_SNORM = 95,
+ SVGA3D_R8_SINT = 96,
+ SVGA3D_P8 = 97,
+ SVGA3D_R9G9B9E5_SHAREDEXP = 98,
+ SVGA3D_R8G8_B8G8_UNORM = 99,
+ SVGA3D_G8R8_G8B8_UNORM = 100,
+ SVGA3D_BC1_TYPELESS = 101,
+ SVGA3D_BC1_UNORM_SRGB = 102,
+ SVGA3D_BC2_TYPELESS = 103,
+ SVGA3D_BC2_UNORM_SRGB = 104,
+ SVGA3D_BC3_TYPELESS = 105,
+ SVGA3D_BC3_UNORM_SRGB = 106,
+ SVGA3D_BC4_TYPELESS = 107,
+ SVGA3D_ATI1 = 108,
+ SVGA3D_BC4_SNORM = 109,
+ SVGA3D_BC5_TYPELESS = 110,
+ SVGA3D_ATI2 = 111,
+ SVGA3D_BC5_SNORM = 112,
+ SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
+ SVGA3D_B8G8R8A8_TYPELESS = 114,
+ SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
+ SVGA3D_B8G8R8X8_TYPELESS = 116,
+ SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
+
+ SVGA3D_Z_DF16 = 118,
+ SVGA3D_Z_DF24 = 119,
+ SVGA3D_Z_D24S8_INT = 120,
+
+ SVGA3D_YV12 = 121,
+
+ SVGA3D_R32G32B32A32_FLOAT = 122,
+ SVGA3D_R16G16B16A16_FLOAT = 123,
+ SVGA3D_R16G16B16A16_UNORM = 124,
+ SVGA3D_R32G32_FLOAT = 125,
+ SVGA3D_R10G10B10A2_UNORM = 126,
+ SVGA3D_R8G8B8A8_SNORM = 127,
+ SVGA3D_R16G16_FLOAT = 128,
+ SVGA3D_R16G16_UNORM = 129,
+ SVGA3D_R16G16_SNORM = 130,
+ SVGA3D_R32_FLOAT = 131,
+ SVGA3D_R8G8_SNORM = 132,
+ SVGA3D_R16_FLOAT = 133,
+ SVGA3D_D16_UNORM = 134,
+ SVGA3D_A8_UNORM = 135,
+ SVGA3D_BC1_UNORM = 136,
+ SVGA3D_BC2_UNORM = 137,
+ SVGA3D_BC3_UNORM = 138,
+ SVGA3D_B5G6R5_UNORM = 139,
+ SVGA3D_B5G5R5A1_UNORM = 140,
+ SVGA3D_B8G8R8A8_UNORM = 141,
+ SVGA3D_B8G8R8X8_UNORM = 142,
+ SVGA3D_BC4_UNORM = 143,
+ SVGA3D_BC5_UNORM = 144,
+ SVGA3D_B4G4R4A4_UNORM = 145,
+
+ SVGA3D_BC6H_TYPELESS = 146,
+ SVGA3D_BC6H_UF16 = 147,
+ SVGA3D_BC6H_SF16 = 148,
+ SVGA3D_BC7_TYPELESS = 149,
+ SVGA3D_BC7_UNORM = 150,
+ SVGA3D_BC7_UNORM_SRGB = 151,
+
+ SVGA3D_AYUV = 152,
+
+ SVGA3D_R11G11B10_TYPELESS = 153,
+
+ SVGA3D_FORMAT_MAX
} SVGA3dSurfaceFormat;
-/*
- * SVGA3d Surface Flags --
- */
-#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
+#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
-/*
- * HINT flags are not enforced by the device but are useful for
- * performance.
- */
-#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
-#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
-#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
-#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
-#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
-#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
-#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
-#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
-#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9)
-#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
-
-#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11)
+#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
+#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
+#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
+#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
+#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
+#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
+#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
+#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
+#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9)
+#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
-/*
- * Is this surface using a base-level pitch for it's mob backing?
- *
- * This flag is not intended to be set by guest-drivers, but is instead
- * set by the device when the surface is bound to a mob with a specified
- * pitch.
- */
-#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
+#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11)
-#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
-#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
-#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
+#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
-/*
- * Required to be set on a surface to bind it to a screen target.
- */
-#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
+#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
+#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
+#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
-/*
- * Align images in the guest-backing mob to 16-bytes.
- */
-#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
+#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
-#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
-#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
+#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
-/*
- * Bind flags.
- * These are enforced for any surface defined with DefineGBSurface_v2.
- */
-#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
-#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
-#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
-#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
-#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
-#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
-#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
+#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
+#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
-/*
- * The STAGING flags notes that the surface will not be used directly by the
- * drawing pipeline, i.e. that it will not be bound to any bind point.
- * Staging surfaces may be used by copy operations to move data in and out
- * of other surfaces. No bind flags may be set on surfaces with this flag.
- *
- * The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
- * updates indirectly, i.e. the surface will not be updated directly, but
- * will receive copies from staging surfaces.
- */
-#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
-#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
-#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
+#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
+#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
+#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
+#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
+#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
+#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
+#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
-/*
- * Setting this flag allow this surface to be used with the
- * SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
- * buffer surfaces, and no bind flags are allowed to be set on surfaces
- * with this flag except SVGA3D_SURFACE_TRANSFER_TO_BUFFER.
- */
-#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
+#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
+#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
+#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
-/*
- * Reserved for video operations.
- */
-#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
+#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
-/*
- * Specifies that a surface is multisample, and therefore requires the full
- * mob-backing to store all the samples.
- */
-#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
+#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
+#define SVGA3D_SURFACE_VADECODE SVGA3D_SURFACE_RESERVED1
-/*
- * Specified that the surface is allowed to be bound to a UAView.
- */
-#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33)
+#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
-/*
- * Setting this flag allow this surface to be used with the
- * SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER command. It is only valid for
- * buffer surfaces, and no bind flags are allowed to be set on surfaces
- * with this flag except SVGA3D_SURFACE_TRANSFER_FROM_BUFFER.
- */
-#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34)
+#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33)
-#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35)
+#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34)
-/*
- * Optional flags for use with SVGA3D_SURFACE_BIND_UAVIEW
- */
-#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36)
-#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37)
+#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35)
-#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38)
-#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39)
+#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36)
+#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37)
-#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 40)
+#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38)
+#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39)
+
+#define SVGA3D_SURFACE_STAGING_COPY (CONST64U(1) << 40)
+
+#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 44)
-/*
- * Surface flags types:
- *
- * SVGA3dSurface1Flags: Lower 32-bits of flags.
- * SVGA3dSurface2Flags: Upper 32-bits of flags.
- * SVGA3dSurfaceAllFlags: Full 64-bits of flags.
- */
typedef uint32 SVGA3dSurface1Flags;
typedef uint32 SVGA3dSurface2Flags;
typedef uint64 SVGA3dSurfaceAllFlags;
-#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64_t)MAX_UINT32)
+#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64)MAX_UINT32)
#define SVGA3D_SURFACE_FLAGS2_MASK (MAX_UINT64 & ~SVGA3D_SURFACE_FLAGS1_MASK)
-#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_MOB_PITCH | \
- SVGA3D_SURFACE_SCREENTARGET | \
- SVGA3D_SURFACE_ALIGN16 | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_MULTISAMPLE \
- )
-
-#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_MULTISAMPLE \
- )
-
-#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_INACTIVE | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_DEAD2 | \
- SVGA3D_SURFACE_ARRAY | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_MOB_PITCH | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_SCREENTARGET | \
- SVGA3D_SURFACE_MOB_PITCH | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_RESERVED1 | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
- )
-
-#define SVGA3D_SURFACE_DX_ONLY_MASK \
- ( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER \
- )
-
-#define SVGA3D_SURFACE_STAGING_MASK \
- ( SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD \
- )
-
-#define SVGA3D_SURFACE_BIND_MASK \
- ( SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
- SVGA3D_SURFACE_BIND_RENDER_TARGET | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS \
- )
-
-#define SVGA3D_SURFACE_VADECODE_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_HINT_STATIC | \
- SVGA3D_SURFACE_HINT_DYNAMIC | \
- SVGA3D_SURFACE_HINT_INDEXBUFFER | \
- SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
- SVGA3D_SURFACE_HINT_TEXTURE | \
- SVGA3D_SURFACE_HINT_RENDERTARGET | \
- SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
- SVGA3D_SURFACE_HINT_WRITEONLY | \
- SVGA3D_SURFACE_DEAD2 | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_HINT_RT_LOCKABLE | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_SCREENTARGET | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_RENDER_TARGET | \
- SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_INACTIVE | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_VAPROCESSFRAME_OUTPUT_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_HINT_INDEXBUFFER | \
- SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
- SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
- SVGA3D_SURFACE_DEAD2 | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_INACTIVE | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_VADECODE | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_VAPROCESSFRAME_INPUT_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_HINT_INDEXBUFFER | \
- SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
- SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
- SVGA3D_SURFACE_DEAD2 | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_SCREENTARGET | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_STAGING_UPLOAD | \
- SVGA3D_SURFACE_STAGING_DOWNLOAD | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_LOGICOPS | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
-
-#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \
- ( SVGA3D_SURFACE_CUBEMAP | \
- SVGA3D_SURFACE_DEAD2 | \
- SVGA3D_SURFACE_AUTOGENMIPMAPS | \
- SVGA3D_SURFACE_VOLUME | \
- SVGA3D_SURFACE_1D | \
- SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
- SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
- SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
- SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
- SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
- SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
- SVGA3D_SURFACE_VADECODE | \
- SVGA3D_SURFACE_MULTISAMPLE | \
- SVGA3D_SURFACE_BIND_UAVIEW | \
- SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
- SVGA3D_SURFACE_BIND_RAW_VIEWS | \
- SVGA3D_SURFACE_BUFFER_STRUCTURED | \
- SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
- SVGA3D_SURFACE_RESOURCE_CLAMP \
- )
+#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_SCREENTARGET | \
+ SVGA3D_SURFACE_ALIGN16 | SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
+ SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \
+ SVGA3D_SURFACE_STAGING_DOWNLOAD | \
+ SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
+ SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
+ SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
+ SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \
+ SVGA3D_SURFACE_RESTRICT_UPDATE | SVGA3D_SURFACE_BIND_TENSOR | \
+ SVGA3D_SURFACE_LO_STAGING)
+
+#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_1D | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_STAGING_COPY)
+
+#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
+ SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
+ SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
+ SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
+ SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
+ SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
+ SVGA3D_SURFACE_BIND_TENSOR)
+
+#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
+ SVGA3D_SURFACE_MULTISAMPLE)
+
+#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
+ SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
+ SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
+ SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_INACTIVE | \
+ SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \
+ SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
+ SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
+ SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \
+ SVGA3D_SURFACE_BIND_TENSOR | SVGA3D_SURFACE_LO_STAGING)
+
+#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | SVGA3D_SURFACE_DEAD2 | \
+ SVGA3D_SURFACE_ARRAY | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_RESOURCE_CLAMP)
+
+#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
+ SVGA3D_SURFACE_SCREENTARGET | SVGA3D_SURFACE_MOB_PITCH | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_BIND_UAVIEW | \
+ SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_LOGICOPS | \
+ SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
+ SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_STAGING_COPY)
+
+#define SVGA3D_SURFACE_DX_ONLY_MASK \
+ (SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \
+ SVGA3D_SURFACE_STAGING_DOWNLOAD | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
+ SVGA3D_SURFACE_TRANSFER_TO_BUFFER)
+
+#define SVGA3D_SURFACE_ANY_STAGING_MASK \
+ (SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \
+ SVGA3D_SURFACE_STAGING_COPY | SVGA3D_SURFACE_LO_STAGING)
+
+#define SVGA3D_SURFACE_ANY_NONHINT_STAGING_MASK \
+ (SVGA3D_SURFACE_ANY_STAGING_MASK & ~(SVGA3D_SURFACE_LO_STAGING))
+
+#define SVGA3D_SURFACE_BIND_MASK \
+ (SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
+ SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
+ SVGA3D_SURFACE_BIND_RENDER_TARGET | \
+ SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
+ SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_BIND_UAVIEW | \
+ SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
+ SVGA3D_SURFACE_BIND_TENSOR)
+
+#define SVGA3D_SURFACE_STAGING_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_BIND_MASK | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
+ SVGA3D_SURFACE_SCREENTARGET | SVGA3D_SURFACE_HINT_RENDERTARGET | \
+ SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
+ SVGA3D_SURFACE_BIND_TENSOR)
+
+#define SVGA3D_SURFACE_STAGING_COPY_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_STAGING_DISALLOWED_MASK | \
+ SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER)
+
+#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \
+ (SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_DEAD2 | \
+ SVGA3D_SURFACE_AUTOGENMIPMAPS | SVGA3D_SURFACE_VOLUME | \
+ SVGA3D_SURFACE_1D | SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
+ SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
+ SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
+ SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
+ SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
+ SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
+ SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
+ SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
+ SVGA3D_SURFACE_STAGING_COPY)
+
+#define SVGA3D_SURFACE_SM5_MASK \
+ (SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
+ SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BIND_UAVIEW | \
+ SVGA3D_SURFACE_RESOURCE_CLAMP)
#define SVGA3D_BUFFER_STRUCTURED_STRIDE_MAX 2048
-
-/*
- * These are really the D3DFORMAT_OP defines from the wdk. We need
- * them so that we can query the host for what the supported surface
- * operations are (when we're using the D3D backend, in particular),
- * and so we can send those operations to the guest.
- */
typedef enum {
- SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
- SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
- SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
- SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
- SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
- SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
- SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
+ SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
+ SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
+ SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
+ SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
+ SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
+ SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
+ SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
-/*
- * This format can be used as a render target if the current display mode
- * is the same depth if the alpha channel is ignored. e.g. if the device
- * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
- * format op list entry for A8R8G8B8 should have this cap.
- */
- SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
+ SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
-/*
- * This format contains DirectDraw support (including Flip). This flag
- * should not to be set on alpha formats.
- */
- SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
+ SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
-/*
- * The rasterizer can support some level of Direct3D support in this format
- * and implies that the driver can create a Context in this mode (for some
- * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
- * flag must also be set.
- */
- SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
+ SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
-/*
- * This is set for a private format when the driver has put the bpp in
- * the structure.
- */
- SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
+ SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
-/*
- * Indicates that this format can be converted to any RGB format for which
- * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified.
- */
- SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
+ SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
-/*
- * Indicates that this format can be used to create offscreen plain surfaces.
- */
- SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
+ SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
-/*
- * Indicated that this format can be read as an SRGB texture (meaning that the
- * sampler will linearize the looked up data).
- */
- SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
+ SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
-/*
- * Indicates that this format can be used in the bumpmap instructions.
- */
- SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
+ SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
-/*
- * Indicates that this format can be sampled by the displacement map sampler.
- */
- SVGA3DFORMAT_OP_DMAP = 0x00020000,
+ SVGA3DFORMAT_OP_DMAP = 0x00020000,
-/*
- * Indicates that this format cannot be used with texture filtering.
- */
- SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
+ SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
-/*
- * Indicates that format conversions are supported to this RGB format if
- * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
- */
- SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
+ SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
-/*
- * Indicated that this format can be written as an SRGB target
- * (meaning that the pixel pipe will DE-linearize data on output to format)
- */
- SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
+ SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
-/*
- * Indicates that this format cannot be used with alpha blending.
- */
- SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
+ SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
-/*
- * Indicates that the device can auto-generated sublevels for resources
- * of this format.
- */
- SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
+ SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
-/*
- * Indicates that this format can be used by vertex texture sampler.
- */
- SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
+ SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
-/*
- * Indicates that this format supports neither texture coordinate
- * wrap modes, nor mipmapping.
- */
- SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
+ SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
} SVGA3dFormatOp;
-#define SVGA3D_FORMAT_POSITIVE \
- (SVGA3DFORMAT_OP_TEXTURE | \
- SVGA3DFORMAT_OP_VOLUMETEXTURE | \
- SVGA3DFORMAT_OP_CUBETEXTURE | \
- SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
- SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \
- SVGA3DFORMAT_OP_ZSTENCIL | \
- SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
- SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
- SVGA3DFORMAT_OP_DISPLAYMODE | \
- SVGA3DFORMAT_OP_3DACCELERATION | \
- SVGA3DFORMAT_OP_PIXELSIZE | \
- SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
- SVGA3DFORMAT_OP_OFFSCREENPLAIN | \
- SVGA3DFORMAT_OP_SRGBREAD | \
- SVGA3DFORMAT_OP_BUMPMAP | \
- SVGA3DFORMAT_OP_DMAP | \
- SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \
- SVGA3DFORMAT_OP_SRGBWRITE | \
- SVGA3DFORMAT_OP_AUTOGENMIPMAP | \
- SVGA3DFORMAT_OP_VERTEXTEXTURE)
-
-#define SVGA3D_FORMAT_NEGATIVE \
- (SVGA3DFORMAT_OP_NOFILTER | \
- SVGA3DFORMAT_OP_NOALPHABLEND | \
- SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
+#define SVGA3D_FORMAT_POSITIVE \
+ (SVGA3DFORMAT_OP_TEXTURE | SVGA3DFORMAT_OP_VOLUMETEXTURE | \
+ SVGA3DFORMAT_OP_CUBETEXTURE | \
+ SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
+ SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | SVGA3DFORMAT_OP_ZSTENCIL | \
+ SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
+ SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
+ SVGA3DFORMAT_OP_DISPLAYMODE | SVGA3DFORMAT_OP_3DACCELERATION | \
+ SVGA3DFORMAT_OP_PIXELSIZE | SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
+ SVGA3DFORMAT_OP_OFFSCREENPLAIN | SVGA3DFORMAT_OP_SRGBREAD | \
+ SVGA3DFORMAT_OP_BUMPMAP | SVGA3DFORMAT_OP_DMAP | \
+ SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | SVGA3DFORMAT_OP_SRGBWRITE | \
+ SVGA3DFORMAT_OP_AUTOGENMIPMAP | SVGA3DFORMAT_OP_VERTEXTEXTURE)
+
+#define SVGA3D_FORMAT_NEGATIVE \
+ (SVGA3DFORMAT_OP_NOFILTER | SVGA3DFORMAT_OP_NOALPHABLEND | \
+ SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
-/*
- * This structure is a conversion of SVGA3DFORMAT_OP_*
- * Entries must be located at the same position.
- */
typedef union {
- uint32 value;
- struct {
- uint32 texture : 1;
- uint32 volumeTexture : 1;
- uint32 cubeTexture : 1;
- uint32 offscreenRenderTarget : 1;
- uint32 sameFormatRenderTarget : 1;
- uint32 unknown1 : 1;
- uint32 zStencil : 1;
- uint32 zStencilArbitraryDepth : 1;
- uint32 sameFormatUpToAlpha : 1;
- uint32 unknown2 : 1;
- uint32 displayMode : 1;
- uint32 acceleration3d : 1;
- uint32 pixelSize : 1;
- uint32 convertToARGB : 1;
- uint32 offscreenPlain : 1;
- uint32 sRGBRead : 1;
- uint32 bumpMap : 1;
- uint32 dmap : 1;
- uint32 noFilter : 1;
- uint32 memberOfGroupARGB : 1;
- uint32 sRGBWrite : 1;
- uint32 noAlphaBlend : 1;
- uint32 autoGenMipMap : 1;
- uint32 vertexTexture : 1;
- uint32 noTexCoordWrapNorMip : 1;
- };
+ uint32 value;
+ struct {
+ uint32 texture : 1;
+ uint32 volumeTexture : 1;
+ uint32 cubeTexture : 1;
+ uint32 offscreenRenderTarget : 1;
+ uint32 sameFormatRenderTarget : 1;
+ uint32 unknown1 : 1;
+ uint32 zStencil : 1;
+ uint32 zStencilArbitraryDepth : 1;
+ uint32 sameFormatUpToAlpha : 1;
+ uint32 unknown2 : 1;
+ uint32 displayMode : 1;
+ uint32 acceleration3d : 1;
+ uint32 pixelSize : 1;
+ uint32 convertToARGB : 1;
+ uint32 offscreenPlain : 1;
+ uint32 sRGBRead : 1;
+ uint32 bumpMap : 1;
+ uint32 dmap : 1;
+ uint32 noFilter : 1;
+ uint32 memberOfGroupARGB : 1;
+ uint32 sRGBWrite : 1;
+ uint32 noAlphaBlend : 1;
+ uint32 autoGenMipMap : 1;
+ uint32 vertexTexture : 1;
+ uint32 noTexCoordWrapNorMip : 1;
+ };
} SVGA3dSurfaceFormatCaps;
-/*
- * SVGA_3D_CMD_SETRENDERSTATE Types. All value types
- * must fit in a uint32.
- */
-
typedef enum {
- SVGA3D_RS_INVALID = 0,
- SVGA3D_RS_MIN = 1,
- SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
- SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
- SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
- SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
- SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
- SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
- SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
- SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
- SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
- SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
- SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
- SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
- SVGA3D_RS_STENCILREF = 13, /* uint32 */
- SVGA3D_RS_STENCILMASK = 14, /* uint32 */
- SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
- SVGA3D_RS_FOGSTART = 16, /* float */
- SVGA3D_RS_FOGEND = 17, /* float */
- SVGA3D_RS_FOGDENSITY = 18, /* float */
- SVGA3D_RS_POINTSIZE = 19, /* float */
- SVGA3D_RS_POINTSIZEMIN = 20, /* float */
- SVGA3D_RS_POINTSIZEMAX = 21, /* float */
- SVGA3D_RS_POINTSCALE_A = 22, /* float */
- SVGA3D_RS_POINTSCALE_B = 23, /* float */
- SVGA3D_RS_POINTSCALE_C = 24, /* float */
- SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
- SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
- SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
- SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
- SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
- SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
- SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
- SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
- SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
- SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
- SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
- SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
- SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
- SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
- SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
- SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
- SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
- SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
- SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
- SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
- SVGA3D_RS_ZBIAS = 45, /* float */
- SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
- SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
- SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
- SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
- SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
- SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
- SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
- SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
- SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
- SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
- SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
- SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
- SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
- SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
- SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
- SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
- SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
- SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
- SVGA3D_RS_DEPTHBIAS = 64, /* float */
-
-
- /*
- * Output Gamma Level
- *
- * Output gamma effects the gamma curve of colors that are output from the
- * rendering pipeline. A value of 1.0 specifies a linear color space. If the
- * value is <= 0.0, gamma correction is ignored and linear color space is
- * used.
- */
-
- SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
- SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
- SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
- SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
- SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
- SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
- SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
- SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
- SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
- SVGA3D_RS_TWEENFACTOR = 88, /* float */
- SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
- SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
- SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
- SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
- SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
- SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
- SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
- SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
- SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
- SVGA3D_RS_LINEWIDTH = 98, /* float */
- SVGA3D_RS_MAX
+ SVGA3D_RS_INVALID = 0,
+ SVGA3D_RS_MIN = 1,
+ SVGA3D_RS_ZENABLE = 1,
+ SVGA3D_RS_ZWRITEENABLE = 2,
+ SVGA3D_RS_ALPHATESTENABLE = 3,
+ SVGA3D_RS_DITHERENABLE = 4,
+ SVGA3D_RS_BLENDENABLE = 5,
+ SVGA3D_RS_FOGENABLE = 6,
+ SVGA3D_RS_SPECULARENABLE = 7,
+ SVGA3D_RS_STENCILENABLE = 8,
+ SVGA3D_RS_LIGHTINGENABLE = 9,
+ SVGA3D_RS_NORMALIZENORMALS = 10,
+ SVGA3D_RS_POINTSPRITEENABLE = 11,
+ SVGA3D_RS_POINTSCALEENABLE = 12,
+ SVGA3D_RS_STENCILREF = 13,
+ SVGA3D_RS_STENCILMASK = 14,
+ SVGA3D_RS_STENCILWRITEMASK = 15,
+ SVGA3D_RS_FOGSTART = 16,
+ SVGA3D_RS_FOGEND = 17,
+ SVGA3D_RS_FOGDENSITY = 18,
+ SVGA3D_RS_POINTSIZE = 19,
+ SVGA3D_RS_POINTSIZEMIN = 20,
+ SVGA3D_RS_POINTSIZEMAX = 21,
+ SVGA3D_RS_POINTSCALE_A = 22,
+ SVGA3D_RS_POINTSCALE_B = 23,
+ SVGA3D_RS_POINTSCALE_C = 24,
+ SVGA3D_RS_FOGCOLOR = 25,
+ SVGA3D_RS_AMBIENT = 26,
+ SVGA3D_RS_CLIPPLANEENABLE = 27,
+ SVGA3D_RS_FOGMODE = 28,
+ SVGA3D_RS_FILLMODE = 29,
+ SVGA3D_RS_SHADEMODE = 30,
+ SVGA3D_RS_LINEPATTERN = 31,
+ SVGA3D_RS_SRCBLEND = 32,
+ SVGA3D_RS_DSTBLEND = 33,
+ SVGA3D_RS_BLENDEQUATION = 34,
+ SVGA3D_RS_CULLMODE = 35,
+ SVGA3D_RS_ZFUNC = 36,
+ SVGA3D_RS_ALPHAFUNC = 37,
+ SVGA3D_RS_STENCILFUNC = 38,
+ SVGA3D_RS_STENCILFAIL = 39,
+ SVGA3D_RS_STENCILZFAIL = 40,
+ SVGA3D_RS_STENCILPASS = 41,
+ SVGA3D_RS_ALPHAREF = 42,
+ SVGA3D_RS_FRONTWINDING = 43,
+ SVGA3D_RS_COORDINATETYPE = 44,
+ SVGA3D_RS_ZBIAS = 45,
+ SVGA3D_RS_RANGEFOGENABLE = 46,
+ SVGA3D_RS_COLORWRITEENABLE = 47,
+ SVGA3D_RS_VERTEXMATERIALENABLE = 48,
+ SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49,
+ SVGA3D_RS_SPECULARMATERIALSOURCE = 50,
+ SVGA3D_RS_AMBIENTMATERIALSOURCE = 51,
+ SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52,
+ SVGA3D_RS_TEXTUREFACTOR = 53,
+ SVGA3D_RS_LOCALVIEWER = 54,
+ SVGA3D_RS_SCISSORTESTENABLE = 55,
+ SVGA3D_RS_BLENDCOLOR = 56,
+ SVGA3D_RS_STENCILENABLE2SIDED = 57,
+ SVGA3D_RS_CCWSTENCILFUNC = 58,
+ SVGA3D_RS_CCWSTENCILFAIL = 59,
+ SVGA3D_RS_CCWSTENCILZFAIL = 60,
+ SVGA3D_RS_CCWSTENCILPASS = 61,
+ SVGA3D_RS_VERTEXBLEND = 62,
+ SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63,
+ SVGA3D_RS_DEPTHBIAS = 64,
+
+ SVGA3D_RS_OUTPUTGAMMA = 65,
+ SVGA3D_RS_ZVISIBLE = 66,
+ SVGA3D_RS_LASTPIXEL = 67,
+ SVGA3D_RS_CLIPPING = 68,
+ SVGA3D_RS_WRAP0 = 69,
+ SVGA3D_RS_WRAP1 = 70,
+ SVGA3D_RS_WRAP2 = 71,
+ SVGA3D_RS_WRAP3 = 72,
+ SVGA3D_RS_WRAP4 = 73,
+ SVGA3D_RS_WRAP5 = 74,
+ SVGA3D_RS_WRAP6 = 75,
+ SVGA3D_RS_WRAP7 = 76,
+ SVGA3D_RS_WRAP8 = 77,
+ SVGA3D_RS_WRAP9 = 78,
+ SVGA3D_RS_WRAP10 = 79,
+ SVGA3D_RS_WRAP11 = 80,
+ SVGA3D_RS_WRAP12 = 81,
+ SVGA3D_RS_WRAP13 = 82,
+ SVGA3D_RS_WRAP14 = 83,
+ SVGA3D_RS_WRAP15 = 84,
+ SVGA3D_RS_MULTISAMPLEANTIALIAS = 85,
+ SVGA3D_RS_MULTISAMPLEMASK = 86,
+ SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87,
+ SVGA3D_RS_TWEENFACTOR = 88,
+ SVGA3D_RS_ANTIALIASEDLINEENABLE = 89,
+ SVGA3D_RS_COLORWRITEENABLE1 = 90,
+ SVGA3D_RS_COLORWRITEENABLE2 = 91,
+ SVGA3D_RS_COLORWRITEENABLE3 = 92,
+ SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93,
+ SVGA3D_RS_SRCBLENDALPHA = 94,
+ SVGA3D_RS_DSTBLENDALPHA = 95,
+ SVGA3D_RS_BLENDEQUATIONALPHA = 96,
+ SVGA3D_RS_TRANSPARENCYANTIALIAS = 97,
+ SVGA3D_RS_LINEWIDTH = 98,
+ SVGA3D_RS_MAX
} SVGA3dRenderStateName;
typedef enum {
- SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
- SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
- SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
- SVGA3D_TRANSPARENCYANTIALIAS_MAX
+ SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
+ SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
+ SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
+ SVGA3D_TRANSPARENCYANTIALIAS_MAX
} SVGA3dTransparencyAntialiasType;
typedef enum {
- SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
- SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
- SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
- SVGA3D_VERTEXMATERIAL_MAX = 3,
+ SVGA3D_VERTEXMATERIAL_NONE = 0,
+ SVGA3D_VERTEXMATERIAL_DIFFUSE = 1,
+ SVGA3D_VERTEXMATERIAL_SPECULAR = 2,
+ SVGA3D_VERTEXMATERIAL_MAX = 3,
} SVGA3dVertexMaterial;
typedef enum {
- SVGA3D_FILLMODE_INVALID = 0,
- SVGA3D_FILLMODE_MIN = 1,
- SVGA3D_FILLMODE_POINT = 1,
- SVGA3D_FILLMODE_LINE = 2,
- SVGA3D_FILLMODE_FILL = 3,
- SVGA3D_FILLMODE_MAX
+ SVGA3D_FILLMODE_INVALID = 0,
+ SVGA3D_FILLMODE_MIN = 1,
+ SVGA3D_FILLMODE_POINT = 1,
+ SVGA3D_FILLMODE_LINE = 2,
+ SVGA3D_FILLMODE_FILL = 3,
+ SVGA3D_FILLMODE_MAX
} SVGA3dFillModeType;
-
-typedef
-#include "vmware_pack_begin.h"
-union {
- struct {
- uint16 mode; /* SVGA3dFillModeType */
- uint16 face; /* SVGA3dFace */
- };
- uint32 uintValue;
-}
-#include "vmware_pack_end.h"
-SVGA3dFillMode;
+#pragma pack(push, 1)
+typedef union {
+ struct {
+ uint16 mode;
+ uint16 face;
+ };
+ uint32 uintValue;
+} SVGA3dFillMode;
+#pragma pack(pop)
typedef enum {
- SVGA3D_SHADEMODE_INVALID = 0,
- SVGA3D_SHADEMODE_FLAT = 1,
- SVGA3D_SHADEMODE_SMOOTH = 2,
- SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
- SVGA3D_SHADEMODE_MAX
+ SVGA3D_SHADEMODE_INVALID = 0,
+ SVGA3D_SHADEMODE_FLAT = 1,
+ SVGA3D_SHADEMODE_SMOOTH = 2,
+ SVGA3D_SHADEMODE_PHONG = 3,
+ SVGA3D_SHADEMODE_MAX
} SVGA3dShadeMode;
-typedef
-#include "vmware_pack_begin.h"
-union {
- struct {
- uint16 repeat;
- uint16 pattern;
- };
- uint32 uintValue;
-}
-#include "vmware_pack_end.h"
-SVGA3dLinePattern;
+#pragma pack(push, 1)
+typedef union {
+ struct {
+ uint16 repeat;
+ uint16 pattern;
+ };
+ uint32 uintValue;
+} SVGA3dLinePattern;
+#pragma pack(pop)
typedef enum {
- SVGA3D_BLENDOP_INVALID = 0,
- SVGA3D_BLENDOP_MIN = 1,
- SVGA3D_BLENDOP_ZERO = 1,
- SVGA3D_BLENDOP_ONE = 2,
- SVGA3D_BLENDOP_SRCCOLOR = 3,
- SVGA3D_BLENDOP_INVSRCCOLOR = 4,
- SVGA3D_BLENDOP_SRCALPHA = 5,
- SVGA3D_BLENDOP_INVSRCALPHA = 6,
- SVGA3D_BLENDOP_DESTALPHA = 7,
- SVGA3D_BLENDOP_INVDESTALPHA = 8,
- SVGA3D_BLENDOP_DESTCOLOR = 9,
- SVGA3D_BLENDOP_INVDESTCOLOR = 10,
- SVGA3D_BLENDOP_SRCALPHASAT = 11,
- SVGA3D_BLENDOP_BLENDFACTOR = 12,
- SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
- SVGA3D_BLENDOP_SRC1COLOR = 14,
- SVGA3D_BLENDOP_INVSRC1COLOR = 15,
- SVGA3D_BLENDOP_SRC1ALPHA = 16,
- SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
- SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
- SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
- SVGA3D_BLENDOP_MAX
+ SVGA3D_BLENDOP_INVALID = 0,
+ SVGA3D_BLENDOP_MIN = 1,
+ SVGA3D_BLENDOP_ZERO = 1,
+ SVGA3D_BLENDOP_ONE = 2,
+ SVGA3D_BLENDOP_SRCCOLOR = 3,
+ SVGA3D_BLENDOP_INVSRCCOLOR = 4,
+ SVGA3D_BLENDOP_SRCALPHA = 5,
+ SVGA3D_BLENDOP_INVSRCALPHA = 6,
+ SVGA3D_BLENDOP_DESTALPHA = 7,
+ SVGA3D_BLENDOP_INVDESTALPHA = 8,
+ SVGA3D_BLENDOP_DESTCOLOR = 9,
+ SVGA3D_BLENDOP_INVDESTCOLOR = 10,
+ SVGA3D_BLENDOP_SRCALPHASAT = 11,
+ SVGA3D_BLENDOP_BLENDFACTOR = 12,
+ SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
+ SVGA3D_BLENDOP_SRC1COLOR = 14,
+ SVGA3D_BLENDOP_INVSRC1COLOR = 15,
+ SVGA3D_BLENDOP_SRC1ALPHA = 16,
+ SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
+ SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
+ SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
+ SVGA3D_BLENDOP_MAX
} SVGA3dBlendOp;
typedef enum {
- SVGA3D_BLENDEQ_INVALID = 0,
- SVGA3D_BLENDEQ_MIN = 1,
- SVGA3D_BLENDEQ_ADD = 1,
- SVGA3D_BLENDEQ_SUBTRACT = 2,
- SVGA3D_BLENDEQ_REVSUBTRACT = 3,
- SVGA3D_BLENDEQ_MINIMUM = 4,
- SVGA3D_BLENDEQ_MAXIMUM = 5,
- SVGA3D_BLENDEQ_MAX
+ SVGA3D_BLENDEQ_INVALID = 0,
+ SVGA3D_BLENDEQ_MIN = 1,
+ SVGA3D_BLENDEQ_ADD = 1,
+ SVGA3D_BLENDEQ_SUBTRACT = 2,
+ SVGA3D_BLENDEQ_REVSUBTRACT = 3,
+ SVGA3D_BLENDEQ_MINIMUM = 4,
+ SVGA3D_BLENDEQ_MAXIMUM = 5,
+ SVGA3D_BLENDEQ_MAX
} SVGA3dBlendEquation;
typedef enum {
- SVGA3D_DX11_LOGICOP_MIN = 0,
- SVGA3D_DX11_LOGICOP_CLEAR = 0,
- SVGA3D_DX11_LOGICOP_SET = 1,
- SVGA3D_DX11_LOGICOP_COPY = 2,
- SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
- SVGA3D_DX11_LOGICOP_NOOP = 4,
- SVGA3D_DX11_LOGICOP_INVERT = 5,
- SVGA3D_DX11_LOGICOP_AND = 6,
- SVGA3D_DX11_LOGICOP_NAND = 7,
- SVGA3D_DX11_LOGICOP_OR = 8,
- SVGA3D_DX11_LOGICOP_NOR = 9,
- SVGA3D_DX11_LOGICOP_XOR = 10,
- SVGA3D_DX11_LOGICOP_EQUIV = 11,
- SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
- SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
- SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
- SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
- SVGA3D_DX11_LOGICOP_MAX
+ SVGA3D_DX11_LOGICOP_MIN = 0,
+ SVGA3D_DX11_LOGICOP_CLEAR = 0,
+ SVGA3D_DX11_LOGICOP_SET = 1,
+ SVGA3D_DX11_LOGICOP_COPY = 2,
+ SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
+ SVGA3D_DX11_LOGICOP_NOOP = 4,
+ SVGA3D_DX11_LOGICOP_INVERT = 5,
+ SVGA3D_DX11_LOGICOP_AND = 6,
+ SVGA3D_DX11_LOGICOP_NAND = 7,
+ SVGA3D_DX11_LOGICOP_OR = 8,
+ SVGA3D_DX11_LOGICOP_NOR = 9,
+ SVGA3D_DX11_LOGICOP_XOR = 10,
+ SVGA3D_DX11_LOGICOP_EQUIV = 11,
+ SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
+ SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
+ SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
+ SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
+ SVGA3D_DX11_LOGICOP_MAX
} SVGA3dDX11LogicOp;
typedef enum {
- SVGA3D_FRONTWINDING_INVALID = 0,
- SVGA3D_FRONTWINDING_CW = 1,
- SVGA3D_FRONTWINDING_CCW = 2,
- SVGA3D_FRONTWINDING_MAX
+ SVGA3D_FRONTWINDING_INVALID = 0,
+ SVGA3D_FRONTWINDING_CW = 1,
+ SVGA3D_FRONTWINDING_MIN = 1,
+ SVGA3D_FRONTWINDING_CCW = 2,
+ SVGA3D_FRONTWINDING_MAX
} SVGA3dFrontWinding;
typedef enum {
- SVGA3D_FACE_INVALID = 0,
- SVGA3D_FACE_NONE = 1,
- SVGA3D_FACE_MIN = 1,
- SVGA3D_FACE_FRONT = 2,
- SVGA3D_FACE_BACK = 3,
- SVGA3D_FACE_FRONT_BACK = 4,
- SVGA3D_FACE_MAX
+ SVGA3D_FACE_INVALID = 0,
+ SVGA3D_FACE_NONE = 1,
+ SVGA3D_FACE_MIN = 1,
+ SVGA3D_FACE_FRONT = 2,
+ SVGA3D_FACE_BACK = 3,
+ SVGA3D_FACE_FRONT_BACK = 4,
+ SVGA3D_FACE_MAX
} SVGA3dFace;
-/*
- * The order and the values should not be changed
- */
-
typedef enum {
- SVGA3D_CMP_INVALID = 0,
- SVGA3D_CMP_NEVER = 1,
- SVGA3D_CMP_LESS = 2,
- SVGA3D_CMP_EQUAL = 3,
- SVGA3D_CMP_LESSEQUAL = 4,
- SVGA3D_CMP_GREATER = 5,
- SVGA3D_CMP_NOTEQUAL = 6,
- SVGA3D_CMP_GREATEREQUAL = 7,
- SVGA3D_CMP_ALWAYS = 8,
- SVGA3D_CMP_MAX
+ SVGA3D_CMP_INVALID = 0,
+ SVGA3D_CMP_NEVER = 1,
+ SVGA3D_CMP_LESS = 2,
+ SVGA3D_CMP_EQUAL = 3,
+ SVGA3D_CMP_LESSEQUAL = 4,
+ SVGA3D_CMP_GREATER = 5,
+ SVGA3D_CMP_NOTEQUAL = 6,
+ SVGA3D_CMP_GREATEREQUAL = 7,
+ SVGA3D_CMP_ALWAYS = 8,
+ SVGA3D_CMP_MAX
} SVGA3dCmpFunc;
-/*
- * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
- * the fog factor to be specified in the alpha component of the specular
- * (a.k.a. secondary) vertex color.
- */
typedef enum {
- SVGA3D_FOGFUNC_INVALID = 0,
- SVGA3D_FOGFUNC_EXP = 1,
- SVGA3D_FOGFUNC_EXP2 = 2,
- SVGA3D_FOGFUNC_LINEAR = 3,
- SVGA3D_FOGFUNC_PER_VERTEX = 4
+ SVGA3D_FOGFUNC_INVALID = 0,
+ SVGA3D_FOGFUNC_EXP = 1,
+ SVGA3D_FOGFUNC_EXP2 = 2,
+ SVGA3D_FOGFUNC_LINEAR = 3,
+ SVGA3D_FOGFUNC_PER_VERTEX = 4
} SVGA3dFogFunction;
-/*
- * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
- * or per-pixel basis.
- */
typedef enum {
- SVGA3D_FOGTYPE_INVALID = 0,
- SVGA3D_FOGTYPE_VERTEX = 1,
- SVGA3D_FOGTYPE_PIXEL = 2,
- SVGA3D_FOGTYPE_MAX = 3
+ SVGA3D_FOGTYPE_INVALID = 0,
+ SVGA3D_FOGTYPE_VERTEX = 1,
+ SVGA3D_FOGTYPE_PIXEL = 2,
+ SVGA3D_FOGTYPE_MAX = 3
} SVGA3dFogType;
-/*
- * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
- * computed using the eye Z value of each pixel (or vertex), whereas range-
- * based fog is computed using the actual distance (range) to the eye.
- */
typedef enum {
- SVGA3D_FOGBASE_INVALID = 0,
- SVGA3D_FOGBASE_DEPTHBASED = 1,
- SVGA3D_FOGBASE_RANGEBASED = 2,
- SVGA3D_FOGBASE_MAX = 3
+ SVGA3D_FOGBASE_INVALID = 0,
+ SVGA3D_FOGBASE_DEPTHBASED = 1,
+ SVGA3D_FOGBASE_RANGEBASED = 2,
+ SVGA3D_FOGBASE_MAX = 3
} SVGA3dFogBase;
typedef enum {
- SVGA3D_STENCILOP_INVALID = 0,
- SVGA3D_STENCILOP_MIN = 1,
- SVGA3D_STENCILOP_KEEP = 1,
- SVGA3D_STENCILOP_ZERO = 2,
- SVGA3D_STENCILOP_REPLACE = 3,
- SVGA3D_STENCILOP_INCRSAT = 4,
- SVGA3D_STENCILOP_DECRSAT = 5,
- SVGA3D_STENCILOP_INVERT = 6,
- SVGA3D_STENCILOP_INCR = 7,
- SVGA3D_STENCILOP_DECR = 8,
- SVGA3D_STENCILOP_MAX
+ SVGA3D_STENCILOP_INVALID = 0,
+ SVGA3D_STENCILOP_MIN = 1,
+ SVGA3D_STENCILOP_KEEP = 1,
+ SVGA3D_STENCILOP_ZERO = 2,
+ SVGA3D_STENCILOP_REPLACE = 3,
+ SVGA3D_STENCILOP_INCRSAT = 4,
+ SVGA3D_STENCILOP_DECRSAT = 5,
+ SVGA3D_STENCILOP_INVERT = 6,
+ SVGA3D_STENCILOP_INCR = 7,
+ SVGA3D_STENCILOP_DECR = 8,
+ SVGA3D_STENCILOP_MAX
} SVGA3dStencilOp;
typedef enum {
- SVGA3D_CLIPPLANE_0 = (1 << 0),
- SVGA3D_CLIPPLANE_1 = (1 << 1),
- SVGA3D_CLIPPLANE_2 = (1 << 2),
- SVGA3D_CLIPPLANE_3 = (1 << 3),
- SVGA3D_CLIPPLANE_4 = (1 << 4),
- SVGA3D_CLIPPLANE_5 = (1 << 5),
+ SVGA3D_CLIPPLANE_0 = (1 << 0),
+ SVGA3D_CLIPPLANE_1 = (1 << 1),
+ SVGA3D_CLIPPLANE_2 = (1 << 2),
+ SVGA3D_CLIPPLANE_3 = (1 << 3),
+ SVGA3D_CLIPPLANE_4 = (1 << 4),
+ SVGA3D_CLIPPLANE_5 = (1 << 5),
} SVGA3dClipPlanes;
typedef enum {
- SVGA3D_CLEAR_COLOR = 0x1,
- SVGA3D_CLEAR_DEPTH = 0x2,
- SVGA3D_CLEAR_STENCIL = 0x4,
-
- /*
- * Hint only, must be used together with SVGA3D_CLEAR_COLOR. If
- * SVGA3D_CLEAR_DEPTH or SVGA3D_CLEAR_STENCIL bit is set, this
- * bit will be ignored.
- */
- SVGA3D_CLEAR_COLORFILL = 0x8
+ SVGA3D_CLEAR_COLOR = 0x1,
+ SVGA3D_CLEAR_DEPTH = 0x2,
+ SVGA3D_CLEAR_STENCIL = 0x4,
+
+ SVGA3D_CLEAR_COLORFILL = 0x8
} SVGA3dClearFlag;
typedef enum {
- SVGA3D_RT_DEPTH = 0,
- SVGA3D_RT_MIN = 0,
- SVGA3D_RT_STENCIL = 1,
- SVGA3D_RT_COLOR0 = 2,
- SVGA3D_RT_COLOR1 = 3,
- SVGA3D_RT_COLOR2 = 4,
- SVGA3D_RT_COLOR3 = 5,
- SVGA3D_RT_COLOR4 = 6,
- SVGA3D_RT_COLOR5 = 7,
- SVGA3D_RT_COLOR6 = 8,
- SVGA3D_RT_COLOR7 = 9,
- SVGA3D_RT_MAX,
- SVGA3D_RT_INVALID = ((uint32)-1),
+ SVGA3D_RT_DEPTH = 0,
+ SVGA3D_RT_MIN = 0,
+ SVGA3D_RT_STENCIL = 1,
+ SVGA3D_RT_COLOR0 = 2,
+ SVGA3D_RT_COLOR1 = 3,
+ SVGA3D_RT_COLOR2 = 4,
+ SVGA3D_RT_COLOR3 = 5,
+ SVGA3D_RT_COLOR4 = 6,
+ SVGA3D_RT_COLOR5 = 7,
+ SVGA3D_RT_COLOR6 = 8,
+ SVGA3D_RT_COLOR7 = 9,
+ SVGA3D_RT_MAX,
+ SVGA3D_RT_INVALID = ((uint32)-1),
} SVGA3dRenderTargetType;
#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
-typedef
-#include "vmware_pack_begin.h"
-union {
- struct {
- uint32 red : 1;
- uint32 green : 1;
- uint32 blue : 1;
- uint32 alpha : 1;
- };
- uint32 uintValue;
-}
-#include "vmware_pack_end.h"
-SVGA3dColorMask;
+#pragma pack(push, 1)
+typedef union {
+ struct {
+ uint32 red : 1;
+ uint32 green : 1;
+ uint32 blue : 1;
+ uint32 alpha : 1;
+ };
+ uint32 uintValue;
+} SVGA3dColorMask;
+#pragma pack(pop)
typedef enum {
- SVGA3D_VBLEND_DISABLE = 0,
- SVGA3D_VBLEND_1WEIGHT = 1,
- SVGA3D_VBLEND_2WEIGHT = 2,
- SVGA3D_VBLEND_3WEIGHT = 3,
- SVGA3D_VBLEND_MAX = 4,
+ SVGA3D_VBLEND_DISABLE = 0,
+ SVGA3D_VBLEND_1WEIGHT = 1,
+ SVGA3D_VBLEND_2WEIGHT = 2,
+ SVGA3D_VBLEND_3WEIGHT = 3,
+ SVGA3D_VBLEND_MAX = 4,
} SVGA3dVertexBlendFlags;
typedef enum {
- SVGA3D_WRAPCOORD_0 = 1 << 0,
- SVGA3D_WRAPCOORD_1 = 1 << 1,
- SVGA3D_WRAPCOORD_2 = 1 << 2,
- SVGA3D_WRAPCOORD_3 = 1 << 3,
- SVGA3D_WRAPCOORD_ALL = 0xF,
+ SVGA3D_WRAPCOORD_0 = 1 << 0,
+ SVGA3D_WRAPCOORD_1 = 1 << 1,
+ SVGA3D_WRAPCOORD_2 = 1 << 2,
+ SVGA3D_WRAPCOORD_3 = 1 << 3,
+ SVGA3D_WRAPCOORD_ALL = 0xF,
} SVGA3dWrapFlags;
-/*
- * SVGA_3D_CMD_TEXTURESTATE Types. All value types
- * must fit in a uint32.
- */
-
typedef enum {
- SVGA3D_TS_INVALID = 0,
- SVGA3D_TS_MIN = 1,
- SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
- SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
- SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
- SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
- SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
- SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
- SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
- SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
- SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
- SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
- SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
- SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
- SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
- SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
- SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
- SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
- SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
- SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
- SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
- SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
- SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
- SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
- SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
- SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
-
-
- /*
- * Sampler Gamma Level
- *
- * Sampler gamma effects the color of samples taken from the sampler. A
- * value of 1.0 will produce linear samples. If the value is <= 0.0 the
- * gamma value is ignored and a linear space is used.
- */
-
- SVGA3D_TS_GAMMA = 25, /* float */
- SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
- SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
- SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
- SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
- SVGA3D_TS_PREGB_MAX = 30, /* Max value before GBObjects */
- SVGA3D_TS_CONSTANT = 30, /* SVGA3dColor */
- SVGA3D_TS_COLOR_KEY_ENABLE = 31, /* SVGA3dBool */
- SVGA3D_TS_COLOR_KEY = 32, /* SVGA3dColor */
- SVGA3D_TS_MAX
+ SVGA3D_TS_INVALID = 0,
+ SVGA3D_TS_MIN = 1,
+ SVGA3D_TS_BIND_TEXTURE = 1,
+ SVGA3D_TS_COLOROP = 2,
+ SVGA3D_TS_COLORARG1 = 3,
+ SVGA3D_TS_COLORARG2 = 4,
+ SVGA3D_TS_ALPHAOP = 5,
+ SVGA3D_TS_ALPHAARG1 = 6,
+ SVGA3D_TS_ALPHAARG2 = 7,
+ SVGA3D_TS_ADDRESSU = 8,
+ SVGA3D_TS_ADDRESSV = 9,
+ SVGA3D_TS_MIPFILTER = 10,
+ SVGA3D_TS_MAGFILTER = 11,
+ SVGA3D_TS_MINFILTER = 12,
+ SVGA3D_TS_BORDERCOLOR = 13,
+ SVGA3D_TS_TEXCOORDINDEX = 14,
+ SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15,
+ SVGA3D_TS_TEXCOORDGEN = 16,
+ SVGA3D_TS_BUMPENVMAT00 = 17,
+ SVGA3D_TS_BUMPENVMAT01 = 18,
+ SVGA3D_TS_BUMPENVMAT10 = 19,
+ SVGA3D_TS_BUMPENVMAT11 = 20,
+ SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21,
+ SVGA3D_TS_TEXTURE_LOD_BIAS = 22,
+ SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23,
+ SVGA3D_TS_ADDRESSW = 24,
+
+ SVGA3D_TS_GAMMA = 25,
+ SVGA3D_TS_BUMPENVLSCALE = 26,
+ SVGA3D_TS_BUMPENVLOFFSET = 27,
+ SVGA3D_TS_COLORARG0 = 28,
+ SVGA3D_TS_ALPHAARG0 = 29,
+ SVGA3D_TS_PREGB_MAX = 30,
+ SVGA3D_TS_CONSTANT = 30,
+ SVGA3D_TS_COLOR_KEY_ENABLE = 31,
+ SVGA3D_TS_COLOR_KEY = 32,
+ SVGA3D_TS_MAX
} SVGA3dTextureStateName;
typedef enum {
- SVGA3D_TC_INVALID = 0,
- SVGA3D_TC_DISABLE = 1,
- SVGA3D_TC_SELECTARG1 = 2,
- SVGA3D_TC_SELECTARG2 = 3,
- SVGA3D_TC_MODULATE = 4,
- SVGA3D_TC_ADD = 5,
- SVGA3D_TC_ADDSIGNED = 6,
- SVGA3D_TC_SUBTRACT = 7,
- SVGA3D_TC_BLENDTEXTUREALPHA = 8,
- SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
- SVGA3D_TC_BLENDCURRENTALPHA = 10,
- SVGA3D_TC_BLENDFACTORALPHA = 11,
- SVGA3D_TC_MODULATE2X = 12,
- SVGA3D_TC_MODULATE4X = 13,
- SVGA3D_TC_DSDT = 14,
- SVGA3D_TC_DOTPRODUCT3 = 15,
- SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
- SVGA3D_TC_ADDSIGNED2X = 17,
- SVGA3D_TC_ADDSMOOTH = 18,
- SVGA3D_TC_PREMODULATE = 19,
- SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
- SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
- SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
- SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
- SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
- SVGA3D_TC_MULTIPLYADD = 25,
- SVGA3D_TC_LERP = 26,
- SVGA3D_TC_MAX
+ SVGA3D_TC_INVALID = 0,
+ SVGA3D_TC_DISABLE = 1,
+ SVGA3D_TC_SELECTARG1 = 2,
+ SVGA3D_TC_SELECTARG2 = 3,
+ SVGA3D_TC_MODULATE = 4,
+ SVGA3D_TC_ADD = 5,
+ SVGA3D_TC_ADDSIGNED = 6,
+ SVGA3D_TC_SUBTRACT = 7,
+ SVGA3D_TC_BLENDTEXTUREALPHA = 8,
+ SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
+ SVGA3D_TC_BLENDCURRENTALPHA = 10,
+ SVGA3D_TC_BLENDFACTORALPHA = 11,
+ SVGA3D_TC_MODULATE2X = 12,
+ SVGA3D_TC_MODULATE4X = 13,
+ SVGA3D_TC_DSDT = 14,
+ SVGA3D_TC_DOTPRODUCT3 = 15,
+ SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
+ SVGA3D_TC_ADDSIGNED2X = 17,
+ SVGA3D_TC_ADDSMOOTH = 18,
+ SVGA3D_TC_PREMODULATE = 19,
+ SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
+ SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
+ SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
+ SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
+ SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
+ SVGA3D_TC_MULTIPLYADD = 25,
+ SVGA3D_TC_LERP = 26,
+ SVGA3D_TC_MAX
} SVGA3dTextureCombiner;
-#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
+#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) \
+ (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
typedef enum {
- SVGA3D_TEX_ADDRESS_INVALID = 0,
- SVGA3D_TEX_ADDRESS_MIN = 1,
- SVGA3D_TEX_ADDRESS_WRAP = 1,
- SVGA3D_TEX_ADDRESS_MIRROR = 2,
- SVGA3D_TEX_ADDRESS_CLAMP = 3,
- SVGA3D_TEX_ADDRESS_BORDER = 4,
- SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
- SVGA3D_TEX_ADDRESS_EDGE = 6,
- SVGA3D_TEX_ADDRESS_MAX
+ SVGA3D_TEX_ADDRESS_INVALID = 0,
+ SVGA3D_TEX_ADDRESS_MIN = 1,
+ SVGA3D_TEX_ADDRESS_WRAP = 1,
+ SVGA3D_TEX_ADDRESS_MIRROR = 2,
+ SVGA3D_TEX_ADDRESS_CLAMP = 3,
+ SVGA3D_TEX_ADDRESS_BORDER = 4,
+ SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
+ SVGA3D_TEX_ADDRESS_EDGE = 6,
+ SVGA3D_TEX_ADDRESS_MAX
} SVGA3dTextureAddress;
-/*
- * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
- * disabled, and the rasterizer should use the magnification filter instead.
- */
typedef enum {
- SVGA3D_TEX_FILTER_NONE = 0,
- SVGA3D_TEX_FILTER_MIN = 0,
- SVGA3D_TEX_FILTER_NEAREST = 1,
- SVGA3D_TEX_FILTER_LINEAR = 2,
- SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
- SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
- SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
- SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
- SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
- SVGA3D_TEX_FILTER_MAX
+ SVGA3D_TEX_FILTER_NONE = 0,
+ SVGA3D_TEX_FILTER_MIN = 0,
+ SVGA3D_TEX_FILTER_NEAREST = 1,
+ SVGA3D_TEX_FILTER_LINEAR = 2,
+ SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
+ SVGA3D_TEX_FILTER_FLATCUBIC = 4,
+ SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5,
+ SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6,
+ SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7,
+ SVGA3D_TEX_FILTER_MAX
} SVGA3dTextureFilter;
typedef enum {
- SVGA3D_TEX_TRANSFORM_OFF = 0,
- SVGA3D_TEX_TRANSFORM_S = (1 << 0),
- SVGA3D_TEX_TRANSFORM_T = (1 << 1),
- SVGA3D_TEX_TRANSFORM_R = (1 << 2),
- SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
- SVGA3D_TEX_PROJECTED = (1 << 15),
+ SVGA3D_TEX_TRANSFORM_OFF = 0,
+ SVGA3D_TEX_TRANSFORM_S = (1 << 0),
+ SVGA3D_TEX_TRANSFORM_T = (1 << 1),
+ SVGA3D_TEX_TRANSFORM_R = (1 << 2),
+ SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
+ SVGA3D_TEX_PROJECTED = (1 << 15),
} SVGA3dTexTransformFlags;
typedef enum {
- SVGA3D_TEXCOORD_GEN_OFF = 0,
- SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
- SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
- SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
- SVGA3D_TEXCOORD_GEN_SPHERE = 4,
- SVGA3D_TEXCOORD_GEN_MAX
+ SVGA3D_TEXCOORD_GEN_OFF = 0,
+ SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
+ SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
+ SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
+ SVGA3D_TEXCOORD_GEN_SPHERE = 4,
+ SVGA3D_TEXCOORD_GEN_MAX
} SVGA3dTextureCoordGen;
-/*
- * Texture argument constants for texture combiner
- */
typedef enum {
- SVGA3D_TA_INVALID = 0,
- SVGA3D_TA_TFACTOR = 1,
- SVGA3D_TA_PREVIOUS = 2,
- SVGA3D_TA_DIFFUSE = 3,
- SVGA3D_TA_TEXTURE = 4,
- SVGA3D_TA_SPECULAR = 5,
- SVGA3D_TA_CONSTANT = 6,
- SVGA3D_TA_MAX
+ SVGA3D_TA_INVALID = 0,
+ SVGA3D_TA_TFACTOR = 1,
+ SVGA3D_TA_PREVIOUS = 2,
+ SVGA3D_TA_DIFFUSE = 3,
+ SVGA3D_TA_TEXTURE = 4,
+ SVGA3D_TA_SPECULAR = 5,
+ SVGA3D_TA_CONSTANT = 6,
+ SVGA3D_TA_MAX
} SVGA3dTextureArgData;
#define SVGA3D_TM_MASK_LEN 4
-/* Modifiers for texture argument constants defined above. */
typedef enum {
- SVGA3D_TM_NONE = 0,
- SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
- SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
+ SVGA3D_TM_NONE = 0,
+ SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
+ SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
} SVGA3dTextureArgModifier;
-/*
- * Vertex declarations
- *
- * Notes:
- *
- * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
- * draw with any POSITIONT vertex arrays, the programmable vertex
- * pipeline will be implicitly disabled. Drawing will take place as if
- * no vertex shader was bound.
- */
-
typedef enum {
- SVGA3D_DECLUSAGE_POSITION = 0,
- SVGA3D_DECLUSAGE_BLENDWEIGHT,
- SVGA3D_DECLUSAGE_BLENDINDICES,
- SVGA3D_DECLUSAGE_NORMAL,
- SVGA3D_DECLUSAGE_PSIZE,
- SVGA3D_DECLUSAGE_TEXCOORD,
- SVGA3D_DECLUSAGE_TANGENT,
- SVGA3D_DECLUSAGE_BINORMAL,
- SVGA3D_DECLUSAGE_TESSFACTOR,
- SVGA3D_DECLUSAGE_POSITIONT,
- SVGA3D_DECLUSAGE_COLOR,
- SVGA3D_DECLUSAGE_FOG,
- SVGA3D_DECLUSAGE_DEPTH,
- SVGA3D_DECLUSAGE_SAMPLE,
- SVGA3D_DECLUSAGE_MAX
+ SVGA3D_DECLUSAGE_POSITION = 0,
+ SVGA3D_DECLUSAGE_BLENDWEIGHT,
+ SVGA3D_DECLUSAGE_BLENDINDICES,
+ SVGA3D_DECLUSAGE_NORMAL,
+ SVGA3D_DECLUSAGE_PSIZE,
+ SVGA3D_DECLUSAGE_TEXCOORD,
+ SVGA3D_DECLUSAGE_TANGENT,
+ SVGA3D_DECLUSAGE_BINORMAL,
+ SVGA3D_DECLUSAGE_TESSFACTOR,
+ SVGA3D_DECLUSAGE_POSITIONT,
+ SVGA3D_DECLUSAGE_COLOR,
+ SVGA3D_DECLUSAGE_FOG,
+ SVGA3D_DECLUSAGE_DEPTH,
+ SVGA3D_DECLUSAGE_SAMPLE,
+ SVGA3D_DECLUSAGE_MAX
} SVGA3dDeclUsage;
typedef enum {
- SVGA3D_DECLMETHOD_DEFAULT = 0,
- SVGA3D_DECLMETHOD_PARTIALU,
- SVGA3D_DECLMETHOD_PARTIALV,
- SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
- SVGA3D_DECLMETHOD_UV,
- SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
- SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement */
- /* map */
+ SVGA3D_DECLMETHOD_DEFAULT = 0,
+ SVGA3D_DECLMETHOD_PARTIALU,
+ SVGA3D_DECLMETHOD_PARTIALV,
+ SVGA3D_DECLMETHOD_CROSSUV,
+ SVGA3D_DECLMETHOD_UV,
+ SVGA3D_DECLMETHOD_LOOKUP,
+ SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED,
} SVGA3dDeclMethod;
typedef enum {
- SVGA3D_DECLTYPE_FLOAT1 = 0,
- SVGA3D_DECLTYPE_FLOAT2 = 1,
- SVGA3D_DECLTYPE_FLOAT3 = 2,
- SVGA3D_DECLTYPE_FLOAT4 = 3,
- SVGA3D_DECLTYPE_D3DCOLOR = 4,
- SVGA3D_DECLTYPE_UBYTE4 = 5,
- SVGA3D_DECLTYPE_SHORT2 = 6,
- SVGA3D_DECLTYPE_SHORT4 = 7,
- SVGA3D_DECLTYPE_UBYTE4N = 8,
- SVGA3D_DECLTYPE_SHORT2N = 9,
- SVGA3D_DECLTYPE_SHORT4N = 10,
- SVGA3D_DECLTYPE_USHORT2N = 11,
- SVGA3D_DECLTYPE_USHORT4N = 12,
- SVGA3D_DECLTYPE_UDEC3 = 13,
- SVGA3D_DECLTYPE_DEC3N = 14,
- SVGA3D_DECLTYPE_FLOAT16_2 = 15,
- SVGA3D_DECLTYPE_FLOAT16_4 = 16,
- SVGA3D_DECLTYPE_MAX,
+ SVGA3D_DECLTYPE_FLOAT1 = 0,
+ SVGA3D_DECLTYPE_FLOAT2 = 1,
+ SVGA3D_DECLTYPE_FLOAT3 = 2,
+ SVGA3D_DECLTYPE_FLOAT4 = 3,
+ SVGA3D_DECLTYPE_D3DCOLOR = 4,
+ SVGA3D_DECLTYPE_UBYTE4 = 5,
+ SVGA3D_DECLTYPE_SHORT2 = 6,
+ SVGA3D_DECLTYPE_SHORT4 = 7,
+ SVGA3D_DECLTYPE_UBYTE4N = 8,
+ SVGA3D_DECLTYPE_SHORT2N = 9,
+ SVGA3D_DECLTYPE_SHORT4N = 10,
+ SVGA3D_DECLTYPE_USHORT2N = 11,
+ SVGA3D_DECLTYPE_USHORT4N = 12,
+ SVGA3D_DECLTYPE_UDEC3 = 13,
+ SVGA3D_DECLTYPE_DEC3N = 14,
+ SVGA3D_DECLTYPE_FLOAT16_2 = 15,
+ SVGA3D_DECLTYPE_FLOAT16_4 = 16,
+ SVGA3D_DECLTYPE_MAX,
} SVGA3dDeclType;
-/*
- * This structure is used for the divisor for geometry instancing;
- * it's a direct translation of the Direct3D equivalent.
- */
typedef union {
- struct {
- /*
- * For index data, this number represents the number of instances to draw.
- * For instance data, this number represents the number of
- * instances/vertex in this stream
- */
- uint32 count : 30;
-
- /*
- * This is 1 if this is supposed to be the data that is repeated for
- * every instance.
- */
- uint32 indexedData : 1;
-
- /*
- * This is 1 if this is supposed to be the per-instance data.
- */
- uint32 instanceData : 1;
- };
-
- uint32 value;
+ struct {
+ uint32 count : 30;
+
+ uint32 indexedData : 1;
+
+ uint32 instanceData : 1;
+ };
+
+ uint32 value;
} SVGA3dVertexDivisor;
typedef enum {
- /*
- * SVGA3D_PRIMITIVE_INVALID is a valid primitive type.
- *
- * List MIN second so debuggers will think INVALID is
- * the correct name.
- */
- SVGA3D_PRIMITIVE_INVALID = 0,
- SVGA3D_PRIMITIVE_MIN = 0,
- SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
- SVGA3D_PRIMITIVE_POINTLIST = 2,
- SVGA3D_PRIMITIVE_LINELIST = 3,
- SVGA3D_PRIMITIVE_LINESTRIP = 4,
- SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
- SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
- SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
- SVGA3D_PRIMITIVE_PREDX_MAX = 7,
- SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
- SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
- SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
- SVGA3D_PRIMITIVE_DX10_MAX = 11,
- SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11,
- SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12,
- SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13,
- SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14,
- SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15,
- SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16,
- SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17,
- SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18,
- SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19,
- SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20,
- SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21,
- SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22,
- SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23,
- SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24,
- SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25,
- SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26,
- SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27,
- SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28,
- SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29,
- SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30,
- SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31,
- SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32,
- SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33,
- SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34,
- SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35,
- SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36,
- SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37,
- SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38,
- SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39,
- SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40,
- SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41,
- SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42,
- SVGA3D_PRIMITIVE_MAX = 43
+
+ SVGA3D_PRIMITIVE_INVALID = 0,
+ SVGA3D_PRIMITIVE_MIN = 0,
+ SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
+ SVGA3D_PRIMITIVE_POINTLIST = 2,
+ SVGA3D_PRIMITIVE_LINELIST = 3,
+ SVGA3D_PRIMITIVE_LINESTRIP = 4,
+ SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
+ SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
+ SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
+ SVGA3D_PRIMITIVE_PREDX_MAX = 7,
+ SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
+ SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
+ SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
+ SVGA3D_PRIMITIVE_DX10_MAX = 11,
+ SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11,
+ SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12,
+ SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13,
+ SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14,
+ SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15,
+ SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16,
+ SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17,
+ SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18,
+ SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19,
+ SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20,
+ SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21,
+ SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22,
+ SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23,
+ SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24,
+ SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25,
+ SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26,
+ SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27,
+ SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28,
+ SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29,
+ SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30,
+ SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31,
+ SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32,
+ SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33,
+ SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34,
+ SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35,
+ SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36,
+ SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37,
+ SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38,
+ SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39,
+ SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40,
+ SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41,
+ SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42,
+ SVGA3D_PRIMITIVE_MAX = 43
} SVGA3dPrimitiveType;
typedef enum {
- SVGA3D_COORDINATE_INVALID = 0,
- SVGA3D_COORDINATE_LEFTHANDED = 1,
- SVGA3D_COORDINATE_RIGHTHANDED = 2,
- SVGA3D_COORDINATE_MAX
+ SVGA3D_COORDINATE_INVALID = 0,
+ SVGA3D_COORDINATE_LEFTHANDED = 1,
+ SVGA3D_COORDINATE_RIGHTHANDED = 2,
+ SVGA3D_COORDINATE_MAX
} SVGA3dCoordinateType;
typedef enum {
- SVGA3D_TRANSFORM_INVALID = 0,
- SVGA3D_TRANSFORM_WORLD = 1,
- SVGA3D_TRANSFORM_MIN = 1,
- SVGA3D_TRANSFORM_VIEW = 2,
- SVGA3D_TRANSFORM_PROJECTION = 3,
- SVGA3D_TRANSFORM_TEXTURE0 = 4,
- SVGA3D_TRANSFORM_TEXTURE1 = 5,
- SVGA3D_TRANSFORM_TEXTURE2 = 6,
- SVGA3D_TRANSFORM_TEXTURE3 = 7,
- SVGA3D_TRANSFORM_TEXTURE4 = 8,
- SVGA3D_TRANSFORM_TEXTURE5 = 9,
- SVGA3D_TRANSFORM_TEXTURE6 = 10,
- SVGA3D_TRANSFORM_TEXTURE7 = 11,
- SVGA3D_TRANSFORM_WORLD1 = 12,
- SVGA3D_TRANSFORM_WORLD2 = 13,
- SVGA3D_TRANSFORM_WORLD3 = 14,
- SVGA3D_TRANSFORM_MAX
+ SVGA3D_TRANSFORM_INVALID = 0,
+ SVGA3D_TRANSFORM_WORLD = 1,
+ SVGA3D_TRANSFORM_MIN = 1,
+ SVGA3D_TRANSFORM_VIEW = 2,
+ SVGA3D_TRANSFORM_PROJECTION = 3,
+ SVGA3D_TRANSFORM_TEXTURE0 = 4,
+ SVGA3D_TRANSFORM_TEXTURE1 = 5,
+ SVGA3D_TRANSFORM_TEXTURE2 = 6,
+ SVGA3D_TRANSFORM_TEXTURE3 = 7,
+ SVGA3D_TRANSFORM_TEXTURE4 = 8,
+ SVGA3D_TRANSFORM_TEXTURE5 = 9,
+ SVGA3D_TRANSFORM_TEXTURE6 = 10,
+ SVGA3D_TRANSFORM_TEXTURE7 = 11,
+ SVGA3D_TRANSFORM_WORLD1 = 12,
+ SVGA3D_TRANSFORM_WORLD2 = 13,
+ SVGA3D_TRANSFORM_WORLD3 = 14,
+ SVGA3D_TRANSFORM_MAX
} SVGA3dTransformType;
typedef enum {
- SVGA3D_LIGHTTYPE_INVALID = 0,
- SVGA3D_LIGHTTYPE_MIN = 1,
- SVGA3D_LIGHTTYPE_POINT = 1,
- SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
- SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
- SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
- SVGA3D_LIGHTTYPE_MAX
+ SVGA3D_LIGHTTYPE_INVALID = 0,
+ SVGA3D_LIGHTTYPE_MIN = 1,
+ SVGA3D_LIGHTTYPE_POINT = 1,
+ SVGA3D_LIGHTTYPE_SPOT1 = 2,
+ SVGA3D_LIGHTTYPE_SPOT2 = 3,
+ SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
+ SVGA3D_LIGHTTYPE_MAX
} SVGA3dLightType;
typedef enum {
- SVGA3D_CUBEFACE_POSX = 0,
- SVGA3D_CUBEFACE_NEGX = 1,
- SVGA3D_CUBEFACE_POSY = 2,
- SVGA3D_CUBEFACE_NEGY = 3,
- SVGA3D_CUBEFACE_POSZ = 4,
- SVGA3D_CUBEFACE_NEGZ = 5,
+ SVGA3D_CUBEFACE_POSX = 0,
+ SVGA3D_CUBEFACE_NEGX = 1,
+ SVGA3D_CUBEFACE_POSY = 2,
+ SVGA3D_CUBEFACE_NEGY = 3,
+ SVGA3D_CUBEFACE_POSZ = 4,
+ SVGA3D_CUBEFACE_NEGZ = 5,
} SVGA3dCubeFace;
typedef enum {
- SVGA3D_SHADERTYPE_INVALID = 0,
- SVGA3D_SHADERTYPE_MIN = 1,
- SVGA3D_SHADERTYPE_VS = 1,
- SVGA3D_SHADERTYPE_PS = 2,
- SVGA3D_SHADERTYPE_PREDX_MAX = 3,
- SVGA3D_SHADERTYPE_GS = 3,
- SVGA3D_SHADERTYPE_DX10_MAX = 4,
- SVGA3D_SHADERTYPE_HS = 4,
- SVGA3D_SHADERTYPE_DS = 5,
- SVGA3D_SHADERTYPE_CS = 6,
- SVGA3D_SHADERTYPE_MAX = 7
+ SVGA3D_SHADERTYPE_INVALID = 0,
+ SVGA3D_SHADERTYPE_MIN = 1,
+ SVGA3D_SHADERTYPE_VS = 1,
+ SVGA3D_SHADERTYPE_PS = 2,
+ SVGA3D_SHADERTYPE_PREDX_MAX = 3,
+ SVGA3D_SHADERTYPE_GS = 3,
+ SVGA3D_SHADERTYPE_DX10_MAX = 4,
+ SVGA3D_SHADERTYPE_HS = 4,
+ SVGA3D_SHADERTYPE_DS = 5,
+ SVGA3D_SHADERTYPE_CS = 6,
+ SVGA3D_SHADERTYPE_MAX = 7
} SVGA3dShaderType;
-#define SVGA3D_NUM_SHADERTYPE_PREDX \
- (SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
+#define SVGA3D_NUM_SHADERTYPE_PREDX \
+ (SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
-#define SVGA3D_NUM_SHADERTYPE_DX10 \
- (SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
+#define SVGA3D_NUM_SHADERTYPE_DX10 \
+ (SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
-#define SVGA3D_NUM_SHADERTYPE \
- (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
+#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
typedef enum {
- SVGA3D_CONST_TYPE_MIN = 0,
- SVGA3D_CONST_TYPE_FLOAT = 0,
- SVGA3D_CONST_TYPE_INT = 1,
- SVGA3D_CONST_TYPE_BOOL = 2,
- SVGA3D_CONST_TYPE_MAX = 3,
+ SVGA3D_CONST_TYPE_MIN = 0,
+ SVGA3D_CONST_TYPE_FLOAT = 0,
+ SVGA3D_CONST_TYPE_INT = 1,
+ SVGA3D_CONST_TYPE_BOOL = 2,
+ SVGA3D_CONST_TYPE_MAX = 3,
} SVGA3dShaderConstType;
-/*
- * Register limits for shader consts.
- */
-#define SVGA3D_CONSTREG_MAX 256
-#define SVGA3D_CONSTINTREG_MAX 16
-#define SVGA3D_CONSTBOOLREG_MAX 16
+#define SVGA3D_CONSTREG_MAX 256
+#define SVGA3D_CONSTINTREG_MAX 16
+#define SVGA3D_CONSTBOOLREG_MAX 16
typedef enum {
- SVGA3D_STRETCH_BLT_POINT = 0,
- SVGA3D_STRETCH_BLT_LINEAR = 1,
- SVGA3D_STRETCH_BLT_MAX
+ SVGA3D_STRETCH_BLT_POINT = 0,
+ SVGA3D_STRETCH_BLT_LINEAR = 1,
+ SVGA3D_STRETCH_BLT_MAX
} SVGA3dStretchBltMode;
typedef enum {
- SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
- SVGA3D_QUERYTYPE_MIN = 0,
- SVGA3D_QUERYTYPE_OCCLUSION = 0,
- SVGA3D_QUERYTYPE_TIMESTAMP = 1,
- SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
- SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
- SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
- SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
- SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
- SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
- SVGA3D_QUERYTYPE_DX10_MAX = 8,
- SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8,
- SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9,
- SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10,
- SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11,
- SVGA3D_QUERYTYPE_SOP_STREAM0 = 12,
- SVGA3D_QUERYTYPE_SOP_STREAM1 = 13,
- SVGA3D_QUERYTYPE_SOP_STREAM2 = 14,
- SVGA3D_QUERYTYPE_SOP_STREAM3 = 15,
- SVGA3D_QUERYTYPE_MAX
+ SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
+ SVGA3D_QUERYTYPE_MIN = 0,
+ SVGA3D_QUERYTYPE_OCCLUSION = 0,
+ SVGA3D_QUERYTYPE_TIMESTAMP = 1,
+ SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
+ SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
+ SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
+ SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
+ SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
+ SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
+ SVGA3D_QUERYTYPE_DX10_MAX = 8,
+ SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8,
+ SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9,
+ SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10,
+ SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11,
+ SVGA3D_QUERYTYPE_SOP_STREAM0 = 12,
+ SVGA3D_QUERYTYPE_SOP_STREAM1 = 13,
+ SVGA3D_QUERYTYPE_SOP_STREAM2 = 14,
+ SVGA3D_QUERYTYPE_SOP_STREAM3 = 15,
+ SVGA3D_QUERYTYPE_MAX
} SVGA3dQueryType;
typedef uint8 SVGA3dQueryTypeUint8;
-#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
+#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
-/*
- * This is the maximum number of queries per context that can be active
- * simultaneously between a beginQuery and endQuery.
- */
#define SVGA3D_MAX_QUERY 64
-/*
- * Query result buffer formats
- */
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 samplesRendered;
-}
-#include "vmware_pack_end.h"
-SVGADXOcclusionQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 passed;
-}
-#include "vmware_pack_end.h"
-SVGADXEventQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 timestamp;
-}
-#include "vmware_pack_end.h"
-SVGADXTimestampQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 realFrequency;
- uint32 disjoint;
-}
-#include "vmware_pack_end.h"
-SVGADXTimestampDisjointQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 inputAssemblyVertices;
- uint64 inputAssemblyPrimitives;
- uint64 vertexShaderInvocations;
- uint64 geometryShaderInvocations;
- uint64 geometryShaderPrimitives;
- uint64 clipperInvocations;
- uint64 clipperPrimitives;
- uint64 pixelShaderInvocations;
- uint64 hullShaderInvocations;
- uint64 domainShaderInvocations;
- uint64 computeShaderInvocations;
-}
-#include "vmware_pack_end.h"
-SVGADXPipelineStatisticsQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 anySamplesRendered;
-}
-#include "vmware_pack_end.h"
-SVGADXOcclusionPredicateQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 numPrimitivesWritten;
- uint64 numPrimitivesRequired;
-}
-#include "vmware_pack_end.h"
-SVGADXStreamOutStatisticsQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 overflowed;
-}
-#include "vmware_pack_end.h"
-SVGADXStreamOutPredicateQueryResult;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint64 samplesRendered;
-}
-#include "vmware_pack_end.h"
-SVGADXOcclusion64QueryResult;
-
-/*
- * SVGADXQueryResultUnion is not intended for use in the protocol, but is
- * very helpful when working with queries generically.
- */
-typedef
-#include "vmware_pack_begin.h"
-union SVGADXQueryResultUnion {
- SVGADXOcclusionQueryResult occ;
- SVGADXEventQueryResult event;
- SVGADXTimestampQueryResult ts;
- SVGADXTimestampDisjointQueryResult tsDisjoint;
- SVGADXPipelineStatisticsQueryResult pipelineStats;
- SVGADXOcclusionPredicateQueryResult occPred;
- SVGADXStreamOutStatisticsQueryResult soStats;
- SVGADXStreamOutPredicateQueryResult soPred;
- SVGADXOcclusion64QueryResult occ64;
-}
-#include "vmware_pack_end.h"
-SVGADXQueryResultUnion;
+#pragma pack(push, 1)
+typedef struct {
+ uint32 samplesRendered;
+} SVGADXOcclusionQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 passed;
+} SVGADXEventQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 timestamp;
+} SVGADXTimestampQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 realFrequency;
+ uint32 disjoint;
+} SVGADXTimestampDisjointQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 inputAssemblyVertices;
+ uint64 inputAssemblyPrimitives;
+ uint64 vertexShaderInvocations;
+ uint64 geometryShaderInvocations;
+ uint64 geometryShaderPrimitives;
+ uint64 clipperInvocations;
+ uint64 clipperPrimitives;
+ uint64 pixelShaderInvocations;
+ uint64 hullShaderInvocations;
+ uint64 domainShaderInvocations;
+ uint64 computeShaderInvocations;
+} SVGADXPipelineStatisticsQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 anySamplesRendered;
+} SVGADXOcclusionPredicateQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 numPrimitivesWritten;
+ uint64 numPrimitivesRequired;
+} SVGADXStreamOutStatisticsQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 overflowed;
+} SVGADXStreamOutPredicateQueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint64 samplesRendered;
+} SVGADXOcclusion64QueryResult;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef union SVGADXQueryResultUnion {
+ SVGADXOcclusionQueryResult occ;
+ SVGADXEventQueryResult event;
+ SVGADXTimestampQueryResult ts;
+ SVGADXTimestampDisjointQueryResult tsDisjoint;
+ SVGADXPipelineStatisticsQueryResult pipelineStats;
+ SVGADXOcclusionPredicateQueryResult occPred;
+ SVGADXStreamOutStatisticsQueryResult soStats;
+ SVGADXStreamOutPredicateQueryResult soPred;
+ SVGADXOcclusion64QueryResult occ64;
+} SVGADXQueryResultUnion;
+#pragma pack(pop)
typedef enum {
- SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
- SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
- SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully */
- SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (guest only) */
+ SVGA3D_QUERYSTATE_PENDING = 0,
+ SVGA3D_QUERYSTATE_SUCCEEDED = 1,
+ SVGA3D_QUERYSTATE_FAILED = 2,
+ SVGA3D_QUERYSTATE_NEW = 3,
} SVGA3dQueryState;
typedef enum {
- SVGA3D_WRITE_HOST_VRAM = 1,
- SVGA3D_READ_HOST_VRAM = 2,
+ SVGA3D_WRITE_HOST_VRAM = 1,
+ SVGA3D_READ_HOST_VRAM = 2,
} SVGA3dTransferType;
-#define SVGA3D_LOGICOP_INVALID 0
-#define SVGA3D_LOGICOP_MIN 1
-#define SVGA3D_LOGICOP_COPY 1
-#define SVGA3D_LOGICOP_NOT 2
-#define SVGA3D_LOGICOP_AND 3
-#define SVGA3D_LOGICOP_OR 4
-#define SVGA3D_LOGICOP_XOR 5
-#define SVGA3D_LOGICOP_NXOR 6
-#define SVGA3D_LOGICOP_ROP3 7
-#define SVGA3D_LOGICOP_MAX 8
+#define SVGA3D_LOGICOP_INVALID 0
+#define SVGA3D_LOGICOP_COPY 1
+
+#define SVGA3D_LOGICOP_MIN 1
+#define SVGA3D_LOGICOP_NOT 2
+#define SVGA3D_LOGICOP_AND 3
+#define SVGA3D_LOGICOP_OR 4
+#define SVGA3D_LOGICOP_XOR 5
+#define SVGA3D_LOGICOP_NXOR 6
+#define SVGA3D_LOGICOP_ROP3 7
+
+#define SVGA3D_LOGICOP_MAX 8
typedef uint16 SVGA3dLogicOp;
-#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16) -1)
-#define SVGA3D_LOGICOP_ROP3_MIN 0
-#define SVGA3D_LOGICOP_ROP3_MAX 256
+#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16)-1)
+#define SVGA3D_LOGICOP_ROP3_MIN 0
+#define SVGA3D_LOGICOP_ROP3_MAX 256
typedef uint16 SVGA3dLogicOpRop3;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- union {
- struct {
- uint16 function; // SVGA3dFogFunction
- uint8 type; // SVGA3dFogType
- uint8 base; // SVGA3dFogBase
- };
- uint32 uintValue;
- };
-}
-#include "vmware_pack_end.h"
-SVGA3dFogMode;
-
-/*
- * Uniquely identify one image (a 1D/2D/3D array) from a surface. This
- * is a surface ID as well as face/mipmap indices.
- */
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dSurfaceImageId {
- uint32 sid;
- uint32 face;
- uint32 mipmap;
-}
-#include "vmware_pack_end.h"
-SVGA3dSurfaceImageId;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGA3dSubSurfaceId {
- uint32 sid;
- uint32 subResourceId;
-}
-#include "vmware_pack_end.h"
-SVGA3dSubSurfaceId;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 width;
- uint32 height;
- uint32 depth;
-}
-#include "vmware_pack_end.h"
-SVGA3dSize;
+#pragma pack(push, 1)
+typedef struct {
+ union {
+ struct {
+ uint16 function;
+ uint8 type;
+ uint8 base;
+ };
+ uint32 uintValue;
+ };
+} SVGA3dFogMode;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dSurfaceImageId {
+ uint32 sid;
+ uint32 face;
+ uint32 mipmap;
+} SVGA3dSurfaceImageId;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGA3dSubSurfaceId {
+ uint32 sid;
+ uint32 subResourceId;
+} SVGA3dSubSurfaceId;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 width;
+ uint32 height;
+ uint32 depth;
+} SVGA3dSize;
+#pragma pack(pop)
-/*
- * Guest-backed objects definitions.
- */
typedef enum {
- SVGA_OTABLE_MOB = 0,
- SVGA_OTABLE_MIN = 0,
- SVGA_OTABLE_SURFACE = 1,
- SVGA_OTABLE_CONTEXT = 2,
- SVGA_OTABLE_SHADER = 3,
- SVGA_OTABLE_SCREENTARGET = 4,
-
- SVGA_OTABLE_DX9_MAX = 5,
-
- SVGA_OTABLE_DXCONTEXT = 5,
- SVGA_OTABLE_DX_MAX = 6,
-
- SVGA_OTABLE_RESERVED1 = 6,
- SVGA_OTABLE_RESERVED2 = 7,
-
- /*
- * Additions to this table need to be tied to HW-version features and
- * checkpointed accordingly.
- */
- SVGA_OTABLE_DEVEL_MAX = 8,
- SVGA_OTABLE_MAX = 8
+ SVGA_OTABLE_MOB = 0,
+ SVGA_OTABLE_MIN = 0,
+ SVGA_OTABLE_SURFACE = 1,
+ SVGA_OTABLE_CONTEXT = 2,
+ SVGA_OTABLE_SHADER = 3,
+ SVGA_OTABLE_SCREENTARGET = 4,
+
+ SVGA_OTABLE_DX9_MAX = 5,
+
+ SVGA_OTABLE_DXCONTEXT = 5,
+ SVGA_OTABLE_DX_MAX = 6,
+
+ SVGA_OTABLE_DEVEL_MAX = 6,
+ SVGA_OTABLE_MAX = 6,
+
+ SVGA_OTABLE_RESERVED1 = 6,
+ SVGA_OTABLE_RESERVED2 = 7,
+ SVGA_OTABLE_BUG_1952836_MAX = 8,
} SVGAOTableType;
typedef enum {
- SVGA_COTABLE_MIN = 0,
- SVGA_COTABLE_RTVIEW = 0,
- SVGA_COTABLE_DSVIEW = 1,
- SVGA_COTABLE_SRVIEW = 2,
- SVGA_COTABLE_ELEMENTLAYOUT = 3,
- SVGA_COTABLE_BLENDSTATE = 4,
- SVGA_COTABLE_DEPTHSTENCIL = 5,
- SVGA_COTABLE_RASTERIZERSTATE = 6,
- SVGA_COTABLE_SAMPLER = 7,
- SVGA_COTABLE_STREAMOUTPUT = 8,
- SVGA_COTABLE_DXQUERY = 9,
- SVGA_COTABLE_DXSHADER = 10,
- SVGA_COTABLE_DX10_MAX = 11,
- SVGA_COTABLE_UAVIEW = 11,
- SVGA_COTABLE_MAX = 12,
+ SVGA_COTABLE_MIN = 0,
+ SVGA_COTABLE_RTVIEW = 0,
+ SVGA_COTABLE_DSVIEW = 1,
+ SVGA_COTABLE_SRVIEW = 2,
+ SVGA_COTABLE_ELEMENTLAYOUT = 3,
+ SVGA_COTABLE_BLENDSTATE = 4,
+ SVGA_COTABLE_DEPTHSTENCIL = 5,
+ SVGA_COTABLE_RASTERIZERSTATE = 6,
+ SVGA_COTABLE_SAMPLER = 7,
+ SVGA_COTABLE_STREAMOUTPUT = 8,
+ SVGA_COTABLE_DXQUERY = 9,
+ SVGA_COTABLE_DXSHADER = 10,
+ SVGA_COTABLE_DX10_MAX = 11,
+ SVGA_COTABLE_UAVIEW = 11,
+ SVGA_COTABLE_MAX = 12,
} SVGACOTableType;
-/*
- * The largest size (number of entries) allowed in a COTable.
- */
#define SVGA_COTABLE_MAX_IDS (MAX_UINT16 - 2)
typedef enum SVGAMobFormat {
- SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
- SVGA3D_MOBFMT_PTDEPTH_0 = 0,
- SVGA3D_MOBFMT_MIN = 0,
- SVGA3D_MOBFMT_PTDEPTH_1 = 1,
- SVGA3D_MOBFMT_PTDEPTH_2 = 2,
- SVGA3D_MOBFMT_RANGE = 3,
- SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
- SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
- SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
- SVGA3D_MOBFMT_PREDX_MAX = 7,
- SVGA3D_MOBFMT_EMPTY = 7,
- SVGA3D_MOBFMT_MAX,
-
- /*
- * This isn't actually used by the guest, but is a mob-format used
- * internally by the SVGA device (and is therefore not binary compatible).
- */
- SVGA3D_MOBFMT_HB,
+ SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
+ SVGA3D_MOBFMT_PT_0 = 0,
+ SVGA3D_MOBFMT_MIN = 0,
+ SVGA3D_MOBFMT_PT_1 = 1,
+ SVGA3D_MOBFMT_PT_2 = 2,
+ SVGA3D_MOBFMT_RANGE = 3,
+ SVGA3D_MOBFMT_PT64_0 = 4,
+ SVGA3D_MOBFMT_PT64_1 = 5,
+ SVGA3D_MOBFMT_PT64_2 = 6,
+ SVGA3D_MOBFMT_PREDX_MAX = 7,
+ SVGA3D_MOBFMT_EMPTY = 7,
+
+ SVGA3D_MOBFMT_MAX,
+
+ SVGA3D_MOBFMT_HB,
} SVGAMobFormat;
#define SVGA3D_MOB_EMPTY_BASE 1
-/*
- * Multisample pattern types.
- */
-
typedef enum SVGA3dMSPattern {
- SVGA3D_MS_PATTERN_NONE = 0,
- SVGA3D_MS_PATTERN_MIN = 0,
- SVGA3D_MS_PATTERN_STANDARD = 1,
- SVGA3D_MS_PATTERN_CENTER = 2,
- SVGA3D_MS_PATTERN_MAX = 3,
+ SVGA3D_MS_PATTERN_NONE = 0,
+ SVGA3D_MS_PATTERN_MIN = 0,
+ SVGA3D_MS_PATTERN_STANDARD = 1,
+ SVGA3D_MS_PATTERN_CENTER = 2,
+ SVGA3D_MS_PATTERN_MAX = 3,
} SVGA3dMSPattern;
-/*
- * Precision settings for each sample.
- */
-
typedef enum SVGA3dMSQualityLevel {
- SVGA3D_MS_QUALITY_NONE = 0,
- SVGA3D_MS_QUALITY_MIN = 0,
- SVGA3D_MS_QUALITY_FULL = 1,
- SVGA3D_MS_QUALITY_MAX = 2,
+ SVGA3D_MS_QUALITY_NONE = 0,
+ SVGA3D_MS_QUALITY_MIN = 0,
+ SVGA3D_MS_QUALITY_FULL = 1,
+ SVGA3D_MS_QUALITY_RESOLVED = 2,
+ SVGA3D_MS_QUALITY_MAX = 3,
} SVGA3dMSQualityLevel;
-/*
- * Screen Target Update Flags
- */
-
typedef enum SVGA3dFrameUpdateType {
- SVGA3D_FRAME_END = 0,
- SVGA3D_FRAME_PARTIAL = 1,
- SVGA3D_FRAME_UNKNOWN = 2,
- SVGA3D_FRAME_MAX = 3,
+ SVGA3D_FRAME_END = 0,
+ SVGA3D_FRAME_MIN = 0,
+ SVGA3D_FRAME_PARTIAL = 1,
+ SVGA3D_FRAME_UNKNOWN = 2,
+ SVGA3D_FRAME_MAX = 3,
} SVGA3dFrameUpdateType;
-#endif /* _SVGA3D_TYPES_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h b/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
index acb41e28e46fb96a51c4f6bb9bb27acda3b33f75..bf242c21f3524e9523df9ce2993ae2ea44969921 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2007-2015 VMware, Inc.
+ * Copyright 2007,2020 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -30,61 +30,27 @@
* Definitions for our own (vendor-specific) SVGA Escape commands.
*/
-#ifndef _SVGA_ESCAPE_H_
-#define _SVGA_ESCAPE_H_
-/*
- * Namespace IDs for the escape command
- */
+#ifndef _SVGA_ESCAPE_H_
+#define _SVGA_ESCAPE_H_
#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
-#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
-
+#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
-/*
- * Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
- * the first DWORD of escape data (after the nsID and size). As a
- * guideline we're using the high word and low word as a major and
- * minor command number, respectively.
- *
- * Major command number allocation:
- *
- * 0000: Reserved
- * 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
- * 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
- * 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
- */
-
-#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
-
-
-/*
- * SVGA Hint commands.
- *
- * These escapes let the SVGA driver provide optional information to
- * he host about the state of the guest or guest applications. The
- * host can use these hints to make user interface or performance
- * decisions.
- *
- * Notes:
- *
- * - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
- * that use the SVGA Screen Object extension. Instead of sending
- * this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
- * Screen Object.
- */
+#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
-#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
-#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 /* Deprecated */
+#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
+#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001
-typedef
-struct {
- uint32 command;
- uint32 fullscreen;
- struct {
- int32 x, y;
- } monitorPosition;
+#pragma pack(push, 1)
+typedef struct {
+ uint32 command;
+ uint32 fullscreen;
+ struct {
+ int32 x, y;
+ } monitorPosition;
} SVGAEscapeHintFullscreen;
+#pragma pack(pop)
-#endif /* _SVGA_ESCAPE_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h b/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
index e5385146e7fc3f05adc26fc20c180e0d2e43213b..aec17c3c6c29e30fb55b7c17aac2de452ce979ae 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2007-2015 VMware, Inc.
+ * Copyright 2007-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -30,171 +30,88 @@
* Definitions for video-overlay support.
*/
+
+
#ifndef _SVGA_OVERLAY_H_
#define _SVGA_OVERLAY_H_
#include "svga_reg.h"
-/*
- * Video formats we support
- */
+#if defined __cplusplus
+extern "C" {
+#endif
-#define VMWARE_FOURCC_YV12 0x32315659 /* 'Y' 'V' '1' '2' */
-#define VMWARE_FOURCC_YUY2 0x32595559 /* 'Y' 'U' 'Y' '2' */
-#define VMWARE_FOURCC_UYVY 0x59565955 /* 'U' 'Y' 'V' 'Y' */
+#define VMWARE_FOURCC_YV12 0x32315659
+#define VMWARE_FOURCC_YUY2 0x32595559
+#define VMWARE_FOURCC_UYVY 0x59565955
typedef enum {
- SVGA_OVERLAY_FORMAT_INVALID = 0,
- SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
- SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
- SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
+ SVGA_OVERLAY_FORMAT_INVALID = 0,
+ SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
+ SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
+ SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
} SVGAOverlayFormat;
-#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
+#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
-#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
+#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
-#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
- /* FIFO escape layout:
- * Type, Stream Id, (Register Id, Value) pairs */
+#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
-#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
- /* FIFO escape layout:
- * Type, Stream Id */
+#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
-typedef
-struct SVGAEscapeVideoSetRegs {
- struct {
- uint32 cmdType;
- uint32 streamId;
- } header;
+typedef struct SVGAEscapeVideoSetRegs {
+ struct {
+ uint32 cmdType;
+ uint32 streamId;
+ } header;
- /* May include zero or more items. */
- struct {
- uint32 registerId;
- uint32 value;
- } items[1];
+ struct {
+ uint32 registerId;
+ uint32 value;
+ } items[1];
} SVGAEscapeVideoSetRegs;
-typedef
-struct SVGAEscapeVideoFlush {
- uint32 cmdType;
- uint32 streamId;
+typedef struct SVGAEscapeVideoFlush {
+ uint32 cmdType;
+ uint32 streamId;
} SVGAEscapeVideoFlush;
-
-/*
- * Struct definitions for the video overlay commands built on
- * SVGAFifoCmdEscape.
- */
-typedef
-struct {
- uint32 command;
- uint32 overlay;
+#pragma pack(push, 1)
+typedef struct {
+ uint32 command;
+ uint32 overlay;
} SVGAFifoEscapeCmdVideoBase;
+#pragma pack(pop)
-typedef
-struct {
- SVGAFifoEscapeCmdVideoBase videoCmd;
+#pragma pack(push, 1)
+typedef struct {
+ SVGAFifoEscapeCmdVideoBase videoCmd;
} SVGAFifoEscapeCmdVideoFlush;
-
-typedef
-struct {
- SVGAFifoEscapeCmdVideoBase videoCmd;
- struct {
- uint32 regId;
- uint32 value;
- } items[1];
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAFifoEscapeCmdVideoBase videoCmd;
+ struct {
+ uint32 regId;
+ uint32 value;
+ } items[1];
} SVGAFifoEscapeCmdVideoSetRegs;
-
-typedef
-struct {
- SVGAFifoEscapeCmdVideoBase videoCmd;
- struct {
- uint32 regId;
- uint32 value;
- } items[SVGA_VIDEO_NUM_REGS];
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAFifoEscapeCmdVideoBase videoCmd;
+ struct {
+ uint32 regId;
+ uint32 value;
+ } items[SVGA_VIDEO_NUM_REGS];
} SVGAFifoEscapeCmdVideoSetAllRegs;
+#pragma pack(pop)
-
-/*
- *----------------------------------------------------------------------
- *
- * VMwareVideoGetAttributes --
- *
- * Computes the size, pitches and offsets for YUV frames.
- *
- * Results:
- * TRUE on success; otherwise FALSE on failure.
- *
- * Side effects:
- * Pitches and offsets for the given YUV frame are put in 'pitches'
- * and 'offsets' respectively. They are both optional though.
- *
- *----------------------------------------------------------------------
- */
-
-static inline bool
-VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
- uint32 *width, /* IN / OUT */
- uint32 *height, /* IN / OUT */
- uint32 *size, /* OUT */
- uint32 *pitches, /* OUT (optional) */
- uint32 *offsets) /* OUT (optional) */
-{
- int tmp;
-
- *width = (*width + 1) & ~1;
-
- if (offsets) {
- offsets[0] = 0;
- }
-
- switch (format) {
- case VMWARE_FOURCC_YV12:
- *height = (*height + 1) & ~1;
- *size = (*width) * (*height);
-
- if (pitches) {
- pitches[0] = *width;
- }
-
- if (offsets) {
- offsets[1] = *size;
- }
-
- tmp = *width >> 1;
-
- if (pitches) {
- pitches[1] = pitches[2] = tmp;
- }
-
- tmp *= (*height >> 1);
- *size += tmp;
-
- if (offsets) {
- offsets[2] = *size;
- }
-
- *size += tmp;
- break;
-
- case VMWARE_FOURCC_YUY2:
- case VMWARE_FOURCC_UYVY:
- *size = *width * 2;
-
- if (pitches) {
- pitches[0] = *size;
- }
-
- *size *= *height;
- break;
-
- default:
- return false;
- }
-
- return true;
+#if defined __cplusplus
}
+#endif
-#endif /* _SVGA_OVERLAY_H_ */
+#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
index 193a57f6aae5e7eaf26ad83266759f37c22cd819..b3602557de2e3bd316f357fa9f2cd0c178b8204d 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
* Copyright 1998-2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -30,2277 +30,870 @@
* Virtual hardware definitions for the VMware SVGA II device.
*/
-#ifndef _SVGA_REG_H_
-#define _SVGA_REG_H_
-#include <linux/pci_ids.h>
-#define INCLUDE_ALLOW_MODULE
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
+#ifndef _SVGA_REG_H_
+#define _SVGA_REG_H_
-#include "svga_types.h"
+#include "vm_basic_types.h"
-/*
- * SVGA_REG_ENABLE bit definitions.
- */
typedef enum {
- SVGA_REG_ENABLE_DISABLE = 0,
- SVGA_REG_ENABLE_ENABLE = (1 << 0),
- SVGA_REG_ENABLE_HIDE = (1 << 1),
+ SVGA_REG_ENABLE_DISABLE = 0,
+ SVGA_REG_ENABLE_ENABLE = (1 << 0),
+ SVGA_REG_ENABLE_HIDE = (1 << 1),
} SvgaRegEnable;
typedef uint32 SVGAMobId;
-/*
- * Arbitrary and meaningless limits. Please ignore these when writing
- * new drivers.
- */
-#define SVGA_MAX_WIDTH 2560
-#define SVGA_MAX_HEIGHT 1600
-
+#define SVGA_MAX_WIDTH 2560
+#define SVGA_MAX_HEIGHT 1600
-#define SVGA_MAX_BITS_PER_PIXEL 32
-#define SVGA_MAX_DEPTH 24
-#define SVGA_MAX_DISPLAYS 10
-#define SVGA_MAX_SCREEN_SIZE 8192
+#define SVGA_MAX_BITS_PER_PIXEL 32
+#define SVGA_MAX_DEPTH 24
+#define SVGA_MAX_DISPLAYS 10
+#define SVGA_MAX_SCREEN_SIZE 8192
#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS)
+#define SVGA_CURSOR_ON_HIDE 0x0
+#define SVGA_CURSOR_ON_SHOW 0x1
-/*
- * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
- * cursor bypass mode.
- */
-#define SVGA_CURSOR_ON_HIDE 0x0
-#define SVGA_CURSOR_ON_SHOW 0x1
-
-/*
- * Remove the cursor from the framebuffer
- * because we need to see what's under it
- */
-#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
+#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
-/* Put the cursor back in the framebuffer so the user can see it */
-#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
+#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
-/*
- * The maximum framebuffer size that can traced for guests unless the
- * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case
- * the full framebuffer can be traced independent of this limit.
- */
-#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
+#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
-#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
-#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
-#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
+#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
+#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
+#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
-#define SVGA_MAGIC 0x900000UL
-#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
+#define SVGA_MAGIC 0x900000UL
+#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
-/* Version 3 has the control bar instead of the FIFO */
-#define SVGA_VERSION_3 3
-#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3)
+#define SVGA_VERSION_3 3
+#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3)
-/* Version 2 let the address of the frame buffer be unsigned on Win32 */
-#define SVGA_VERSION_2 2
-#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
+#define SVGA_VERSION_2 2
+#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
-/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
- PALETTE_BASE has moved */
-#define SVGA_VERSION_1 1
-#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
+#define SVGA_VERSION_1 1
+#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
-/* Version 0 is the initial version */
-#define SVGA_VERSION_0 0
-#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
+#define SVGA_VERSION_0 0
+#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
-/*
- * "Invalid" value for all SVGA IDs.
- * (Version ID, screen object ID, surface ID...)
- */
-#define SVGA_ID_INVALID 0xFFFFFFFF
+#define SVGA_ID_INVALID 0xFFFFFFFF
-/* Port offsets, relative to BAR0 */
-#define SVGA_INDEX_PORT 0x0
-#define SVGA_VALUE_PORT 0x1
-#define SVGA_BIOS_PORT 0x2
-#define SVGA_IRQSTATUS_PORT 0x8
+#define SVGA_INDEX_PORT 0x0
+#define SVGA_VALUE_PORT 0x1
+#define SVGA_BIOS_PORT 0x2
+#define SVGA_IRQSTATUS_PORT 0x8
-/*
- * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
- *
- * Interrupts are only supported when the
- * SVGA_CAP_IRQMASK capability is present.
- */
-#define SVGA_IRQFLAG_ANY_FENCE (1 << 0) /* Any fence was passed */
-#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1) /* Made forward progress in the FIFO */
-#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2) /* SVGA_FIFO_FENCE_GOAL reached */
-#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3) /* Command buffer completed */
-#define SVGA_IRQFLAG_ERROR (1 << 4) /* Error while processing commands */
-#define SVGA_IRQFLAG_MAX (1 << 5)
+#define SVGA_IRQFLAG_ANY_FENCE (1 << 0)
+#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1)
+#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2)
+#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3)
+#define SVGA_IRQFLAG_ERROR (1 << 4)
+#define SVGA_IRQFLAG_REG_FENCE_GOAL (1 << 5)
+#define SVGA_IRQFLAG_MAX (1 << 6)
-/*
- * The byte-size is the size of the actual cursor data,
- * possibly after expanding it to the current bit depth.
- *
- * 40K is sufficient memory for two 32-bit planes for a 64 x 64 cursor.
- *
- * The dimension limit is a bound on the maximum width or height.
- */
-#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
+#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024
-/*
- * Registers
- */
-
enum {
- SVGA_REG_ID = 0,
- SVGA_REG_ENABLE = 1,
- SVGA_REG_WIDTH = 2,
- SVGA_REG_HEIGHT = 3,
- SVGA_REG_MAX_WIDTH = 4,
- SVGA_REG_MAX_HEIGHT = 5,
- SVGA_REG_DEPTH = 6,
- SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
- SVGA_REG_PSEUDOCOLOR = 8,
- SVGA_REG_RED_MASK = 9,
- SVGA_REG_GREEN_MASK = 10,
- SVGA_REG_BLUE_MASK = 11,
- SVGA_REG_BYTES_PER_LINE = 12,
- SVGA_REG_FB_START = 13, /* (Deprecated) */
- SVGA_REG_FB_OFFSET = 14,
- SVGA_REG_VRAM_SIZE = 15,
- SVGA_REG_FB_SIZE = 16,
-
- /* ID 0 implementation only had the above registers, then the palette */
- SVGA_REG_ID_0_TOP = 17,
-
- SVGA_REG_CAPABILITIES = 17,
- SVGA_REG_MEM_START = 18, /* (Deprecated) */
- SVGA_REG_MEM_SIZE = 19,
- SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
- SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
- SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
- SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
- SVGA_REG_DEAD = 24, /* Drivers should never write this. */
- SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
- SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
- SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
- SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
- SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
- SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
- SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */
- SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
- SVGA_REG_IRQMASK = 33, /* Interrupt mask */
-
- /* Legacy multi-monitor support */
- SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
- SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */
- SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
- SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
- SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
- SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */
- SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */
-
- /* See "Guest memory regions" below. */
- SVGA_REG_GMR_ID = 41,
- SVGA_REG_GMR_DESCRIPTOR = 42,
- SVGA_REG_GMR_MAX_IDS = 43,
- SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
-
- SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
- SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
- SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
- SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
- SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
-
- /*
- * Max primary memory.
- * See SVGA_CAP_NO_BB_RESTRICTION.
- */
- SVGA_REG_MAX_PRIMARY_MEM = 50,
- SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
-
- /*
- * Legacy version of SVGA_REG_GBOBJECT_MEM_SIZE_KB for drivers that
- * don't know how to convert to a 64-bit byte value without overflowing.
- * (See SVGA_REG_GBOBJECT_MEM_SIZE_KB).
- */
- SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
-
- SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
- SVGA_REG_CMD_PREPEND_LOW = 53,
- SVGA_REG_CMD_PREPEND_HIGH = 54,
- SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
- SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
- SVGA_REG_MOB_MAX_SIZE = 57,
- SVGA_REG_BLANK_SCREEN_TARGETS = 58,
- SVGA_REG_CAP2 = 59,
- SVGA_REG_DEVEL_CAP = 60,
-
- /*
- * Allow the guest to hint to the device which driver is running.
- *
- * This should not generally change device behavior, but might be
- * convenient to work-around specific bugs in guest drivers.
- *
- * Drivers should first write their id value into SVGA_REG_GUEST_DRIVER_ID,
- * and then fill out all of the version registers that they have defined.
- *
- * After the driver has written all of the registers, they should
- * then write the value SVGA_REG_GUEST_DRIVER_ID_SUBMIT to the
- * SVGA_REG_GUEST_DRIVER_ID register, to signal that they have finished.
- *
- * The SVGA_REG_GUEST_DRIVER_ID values are defined below by the
- * SVGARegGuestDriverId enum.
- *
- * The SVGA_REG_GUEST_DRIVER_VERSION fields are driver-specific,
- * but ideally should encode a monotonically increasing number that allows
- * the device to perform inequality checks against ranges of driver versions.
- */
- SVGA_REG_GUEST_DRIVER_ID = 61,
- SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
- SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
- SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
- SVGA_REG_CURSOR_MOBID = 65,
- SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
- SVGA_REG_CURSOR_MAX_DIMENSION = 67,
-
- SVGA_REG_FIFO_CAPS = 68,
- SVGA_REG_FENCE = 69,
-
- SVGA_REG_RESERVED1 = 70,
- SVGA_REG_RESERVED2 = 71,
- SVGA_REG_RESERVED3 = 72,
- SVGA_REG_RESERVED4 = 73,
- SVGA_REG_RESERVED5 = 74,
- SVGA_REG_SCREENDMA = 75,
-
- /*
- * The maximum amount of guest-backed objects that the device can have
- * resident at a time. Guest-drivers should keep their working set size
- * below this limit for best performance.
- *
- * Note that this value is in kilobytes, and not bytes, because the actual
- * number of bytes might be larger than can fit in a 32-bit register.
- *
- * PLEASE USE A 64-BIT VALUE WHEN CONVERTING THIS INTO BYTES.
- * (See SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB).
- */
- SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
-
- /*
- + * These registers are for the addresses of the memory BARs for SVGA3
- */
- SVGA_REG_REGS_START_HIGH32 = 77,
- SVGA_REG_REGS_START_LOW32 = 78,
- SVGA_REG_FB_START_HIGH32 = 79,
- SVGA_REG_FB_START_LOW32 = 80,
-
- /*
- * A hint register that recommends which quality level the guest should
- * currently use to define multisample surfaces.
- *
- * If the register is SVGA_REG_MSHINT_DISABLED,
- * the guest is only allowed to use SVGA3D_MS_QUALITY_FULL.
- *
- * Otherwise, this is a live value that can change while the VM is
- * powered on with the hint suggestion for which quality level the guest
- * should be using. Guests are free to ignore the hint and use either
- * RESOLVE or FULL quality.
- */
- SVGA_REG_MSHINT = 81,
-
- SVGA_REG_IRQ_STATUS = 82,
- SVGA_REG_DIRTY_TRACKING = 83,
-
- SVGA_REG_TOP = 84, /* Must be 1 more than the last register */
-
- SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
- /* Next 768 (== 256*3) registers exist for colormap */
- SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
- /* Base of scratch registers */
- /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
- First 4 are reserved for VESA BIOS Extension; any remaining are for
- the use of the current SVGA driver. */
-};
+ SVGA_REG_ID = 0,
+ SVGA_REG_ENABLE = 1,
+ SVGA_REG_WIDTH = 2,
+ SVGA_REG_HEIGHT = 3,
+ SVGA_REG_MAX_WIDTH = 4,
+ SVGA_REG_MAX_HEIGHT = 5,
+ SVGA_REG_DEPTH = 6,
+ SVGA_REG_BITS_PER_PIXEL = 7,
+ SVGA_REG_PSEUDOCOLOR = 8,
+ SVGA_REG_RED_MASK = 9,
+ SVGA_REG_GREEN_MASK = 10,
+ SVGA_REG_BLUE_MASK = 11,
+ SVGA_REG_BYTES_PER_LINE = 12,
+ SVGA_REG_FB_START = 13,
+ SVGA_REG_FB_OFFSET = 14,
+ SVGA_REG_VRAM_SIZE = 15,
+ SVGA_REG_FB_SIZE = 16,
+
+ SVGA_REG_ID_0_TOP = 17,
+
+ SVGA_REG_CAPABILITIES = 17,
+ SVGA_REG_MEM_START = 18,
+ SVGA_REG_MEM_SIZE = 19,
+ SVGA_REG_CONFIG_DONE = 20,
+ SVGA_REG_SYNC = 21,
+ SVGA_REG_BUSY = 22,
+ SVGA_REG_GUEST_ID = 23,
+ SVGA_REG_DEAD = 24,
+ SVGA_REG_CURSOR_X = 25,
+ SVGA_REG_CURSOR_Y = 26,
+ SVGA_REG_CURSOR_ON = 27,
+ SVGA_REG_HOST_BITS_PER_PIXEL = 28,
+ SVGA_REG_SCRATCH_SIZE = 29,
+ SVGA_REG_MEM_REGS = 30,
+ SVGA_REG_NUM_DISPLAYS = 31,
+ SVGA_REG_PITCHLOCK = 32,
+ SVGA_REG_IRQMASK = 33,
+
+ SVGA_REG_NUM_GUEST_DISPLAYS = 34,
+ SVGA_REG_DISPLAY_ID = 35,
+ SVGA_REG_DISPLAY_IS_PRIMARY = 36,
+ SVGA_REG_DISPLAY_POSITION_X = 37,
+ SVGA_REG_DISPLAY_POSITION_Y = 38,
+ SVGA_REG_DISPLAY_WIDTH = 39,
+ SVGA_REG_DISPLAY_HEIGHT = 40,
+
+ SVGA_REG_GMR_ID = 41,
+ SVGA_REG_GMR_DESCRIPTOR = 42,
+ SVGA_REG_GMR_MAX_IDS = 43,
+ SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
+
+ SVGA_REG_TRACES = 45,
+ SVGA_REG_GMRS_MAX_PAGES = 46,
+ SVGA_REG_MEMORY_SIZE = 47,
+ SVGA_REG_COMMAND_LOW = 48,
+ SVGA_REG_COMMAND_HIGH = 49,
+
+ SVGA_REG_MAX_PRIMARY_MEM = 50,
+
+ SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
+
+ SVGA_REG_DEV_CAP = 52,
+ SVGA_REG_CMD_PREPEND_LOW = 53,
+ SVGA_REG_CMD_PREPEND_HIGH = 54,
+ SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
+ SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
+ SVGA_REG_MOB_MAX_SIZE = 57,
+ SVGA_REG_BLANK_SCREEN_TARGETS = 58,
+ SVGA_REG_CAP2 = 59,
+ SVGA_REG_DEVEL_CAP = 60,
+
+ SVGA_REG_GUEST_DRIVER_ID = 61,
+ SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
+ SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
+ SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
+
+ SVGA_REG_CURSOR_MOBID = 65,
+ SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
+ SVGA_REG_CURSOR_MAX_DIMENSION = 67,
+
+ SVGA_REG_FIFO_CAPS = 68,
+ SVGA_REG_FENCE = 69,
+
+ SVGA_REG_CURSOR4_ON = 70,
+ SVGA_REG_CURSOR4_X = 71,
+ SVGA_REG_CURSOR4_Y = 72,
+ SVGA_REG_CURSOR4_SCREEN_ID = 73,
+ SVGA_REG_CURSOR4_SUBMIT = 74,
+
+ SVGA_REG_SCREENDMA = 75,
+
+ SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
+
+ SVGA_REG_REGS_START_HIGH32 = 77,
+ SVGA_REG_REGS_START_LOW32 = 78,
+ SVGA_REG_FB_START_HIGH32 = 79,
+ SVGA_REG_FB_START_LOW32 = 80,
+
+ SVGA_REG_MSHINT = 81,
+
+ SVGA_REG_IRQ_STATUS = 82,
+
+ SVGA_REG_DIRTY_TRACKING = 83,
+ SVGA_REG_FENCE_GOAL = 84,
+
+ SVGA_REG_TOP = 85,
+
+ SVGA_PALETTE_BASE = 1024,
+
+ SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
+};
-/*
- * Values for SVGA_REG_GUEST_DRIVER_ID.
- */
typedef enum SVGARegGuestDriverId {
- SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
- SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
- SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
- SVGA_REG_GUEST_DRIVER_ID_MAX,
+ SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
+ SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
+ SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
+ SVGA_REG_GUEST_DRIVER_ID_MAX,
- SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
+ SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
} SVGARegGuestDriverId;
typedef enum SVGARegMSHint {
- SVGA_REG_MSHINT_DISABLED = 0,
- SVGA_REG_MSHINT_FULL = 1,
- SVGA_REG_MSHINT_RESOLVED = 2,
+ SVGA_REG_MSHINT_DISABLED = 0,
+ SVGA_REG_MSHINT_FULL = 1,
+ SVGA_REG_MSHINT_RESOLVED = 2,
} SVGARegMSHint;
typedef enum SVGARegDirtyTracking {
- SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0,
- SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1,
+ SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0,
+ SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1,
} SVGARegDirtyTracking;
-
-/*
- * Guest memory regions (GMRs):
- *
- * This is a new memory mapping feature available in SVGA devices
- * which have the SVGA_CAP_GMR bit set. Previously, there were two
- * fixed memory regions available with which to share data between the
- * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
- * are our name for an extensible way of providing arbitrary DMA
- * buffers for use between the driver and the SVGA device. They are a
- * new alternative to framebuffer memory, usable for both 2D and 3D
- * graphics operations.
- *
- * Since GMR mapping must be done synchronously with guest CPU
- * execution, we use a new pair of SVGA registers:
- *
- * SVGA_REG_GMR_ID --
- *
- * Read/write.
- * This register holds the 32-bit ID (a small positive integer)
- * of a GMR to create, delete, or redefine. Writing this register
- * has no side-effects.
- *
- * SVGA_REG_GMR_DESCRIPTOR --
- *
- * Write-only.
- * Writing this register will create, delete, or redefine the GMR
- * specified by the above ID register. If this register is zero,
- * the GMR is deleted. Any pointers into this GMR (including those
- * currently being processed by FIFO commands) will be
- * synchronously invalidated.
- *
- * If this register is nonzero, it must be the physical page
- * number (PPN) of a data structure which describes the physical
- * layout of the memory region this GMR should describe. The
- * descriptor structure will be read synchronously by the SVGA
- * device when this register is written. The descriptor need not
- * remain allocated for the lifetime of the GMR.
- *
- * The guest driver should write SVGA_REG_GMR_ID first, then
- * SVGA_REG_GMR_DESCRIPTOR.
- *
- * SVGA_REG_GMR_MAX_IDS --
- *
- * Read-only.
- * The SVGA device may choose to support a maximum number of
- * user-defined GMR IDs. This register holds the number of supported
- * IDs. (The maximum supported ID plus 1)
- *
- * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
- *
- * Read-only.
- * The SVGA device may choose to put a limit on the total number
- * of SVGAGuestMemDescriptor structures it will read when defining
- * a single GMR.
- *
- * The descriptor structure is an array of SVGAGuestMemDescriptor
- * structures. Each structure may do one of three things:
- *
- * - Terminate the GMR descriptor list.
- * (ppn==0, numPages==0)
- *
- * - Add a PPN or range of PPNs to the GMR's virtual address space.
- * (ppn != 0, numPages != 0)
- *
- * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
- * support multi-page GMR descriptor tables without forcing the
- * driver to allocate physically contiguous memory.
- * (ppn != 0, numPages == 0)
- *
- * Note that each physical page of SVGAGuestMemDescriptor structures
- * can describe at least 2MB of guest memory. If the driver needs to
- * use more than one page of descriptor structures, it must use one of
- * its SVGAGuestMemDescriptors to point to an additional page. The
- * device will never automatically cross a page boundary.
- *
- * Once the driver has described a GMR, it is immediately available
- * for use via any FIFO command that uses an SVGAGuestPtr structure.
- * These pointers include a GMR identifier plus an offset into that
- * GMR.
- *
- * The driver must check the SVGA_CAP_GMR bit before using the GMR
- * registers.
- */
-
-/*
- * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
- * memory as well. In the future, these IDs could even be used to
- * allow legacy memory regions to be redefined by the guest as GMRs.
- *
- * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
- * is being phased out. Please try to use user-defined GMRs whenever
- * possible.
- */
-#define SVGA_GMR_NULL ((uint32) -1)
-#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAGuestMemDescriptor {
- uint32 ppn;
- uint32 numPages;
-}
-#include "vmware_pack_end.h"
-SVGAGuestMemDescriptor;
-
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAGuestPtr {
- uint32 gmrId;
- uint32 offset;
-}
-#include "vmware_pack_end.h"
-SVGAGuestPtr;
-
-/*
- * Register based command buffers --
- *
- * Provide an SVGA device interface that allows the guest to submit
- * command buffers to the SVGA device through an SVGA device register.
- * The metadata for each command buffer is contained in the
- * SVGACBHeader structure along with the return status codes.
- *
- * The SVGA device supports command buffers if
- * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The
- * fifo must be enabled for command buffers to be submitted.
- *
- * Command buffers are submitted when the guest writing the 64 byte
- * aligned physical address into the SVGA_REG_COMMAND_LOW and
- * SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32
- * bits of the physical address. SVGA_REG_COMMAND_LOW contains the
- * lower 32 bits of the physical address, since the command buffer
- * headers are required to be 64 byte aligned the lower 6 bits are
- * used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW
- * submits the command buffer to the device and queues it for
- * execution. The SVGA device supports at least
- * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
- * per context and if that limit is reached the device will write the
- * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
- * buffer header synchronously and not raise any IRQs.
- *
- * It is invalid to submit a command buffer without a valid physical
- * address and results are undefined.
- *
- * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
- * will be supported. If a larger command buffer is submitted results
- * are unspecified and the device will either complete the command
- * buffer or return an error.
- *
- * The device guarantees that any individual command in a command
- * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
- * enough to fit a 64x64 color-cursor definition. If the command is
- * too large the device is allowed to process the command or return an
- * error.
- *
- * The device context is a special SVGACBContext that allows for
- * synchronous register like accesses with the flexibility of
- * commands. There is a different command set defined by
- * SVGADeviceContextCmdId. The commands in each command buffer is not
- * allowed to straddle physical pages.
- *
- * The offset field which is available starting with the
- * SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the
- * start of command processing into the buffer. If an error is
- * encountered the errorOffset will still be relative to the specific
- * PA, not biased by the offset. When the command buffer is finished
- * the guest should not read the offset field as there is no guarantee
- * what it will set to.
- *
- * When the SVGA_CAP_HP_CMD_QUEUE cap bit is set a new command queue
- * SVGA_CB_CONTEXT_1 is available. Commands submitted to this queue
- * will be executed as quickly as possible by the SVGA device
- * potentially before already queued commands on SVGA_CB_CONTEXT_0.
- * The SVGA device guarantees that any command buffers submitted to
- * SVGA_CB_CONTEXT_0 will be executed after any _already_ submitted
- * command buffers to SVGA_CB_CONTEXT_1.
- */
-
-#define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */
+#define SVGA_GMR_NULL ((uint32)-1)
+#define SVGA_GMR_FRAMEBUFFER ((uint32)-2)
+
+#pragma pack(push, 1)
+typedef struct SVGAGuestMemDescriptor {
+ uint32 ppn;
+ uint32 numPages;
+} SVGAGuestMemDescriptor;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct SVGAGuestPtr {
+ uint32 gmrId;
+ uint32 offset;
+} SVGAGuestPtr;
+#pragma pack(pop)
+
+#define SVGA_CB_MAX_SIZE_DEFAULT (KBYTES_2_BYTES(512))
+#define SVGA_CB_MAX_SIZE_4MB (MBYTES_2_BYTES(4))
+#define SVGA_CB_MAX_SIZE SVGA_CB_MAX_SIZE_4MB
#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
-#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
+#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024)
#define SVGA_CB_CONTEXT_MASK 0x3f
typedef enum {
- SVGA_CB_CONTEXT_DEVICE = 0x3f,
- SVGA_CB_CONTEXT_0 = 0x0,
- SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
- SVGA_CB_CONTEXT_MAX = 0x2,
+ SVGA_CB_CONTEXT_DEVICE = 0x3f,
+ SVGA_CB_CONTEXT_0 = 0x0,
+ SVGA_CB_CONTEXT_1 = 0x1,
+ SVGA_CB_CONTEXT_MAX = 0x2,
} SVGACBContext;
-
typedef enum {
- /*
- * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
- * field before submitting the command buffer header, the host will
- * change the value when it is done with the command buffer.
- */
- SVGA_CB_STATUS_NONE = 0,
-
- /*
- * Written by the host when a command buffer completes successfully.
- * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
- * the SVGA_CB_FLAG_NO_IRQ flag is set.
- */
- SVGA_CB_STATUS_COMPLETED = 1,
-
- /*
- * Written by the host synchronously with the command buffer
- * submission to indicate the command buffer was not submitted. No
- * IRQ is raised.
- */
- SVGA_CB_STATUS_QUEUE_FULL = 2,
-
- /*
- * Written by the host when an error was detected parsing a command
- * in the command buffer, errorOffset is written to contain the
- * offset to the first byte of the failing command. The device
- * raises the IRQ with both SVGA_IRQFLAG_ERROR and
- * SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been
- * processed.
- */
- SVGA_CB_STATUS_COMMAND_ERROR = 3,
-
- /*
- * Written by the host if there is an error parsing the command
- * buffer header. The device raises the IRQ with both
- * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device
- * did not processes any of the command buffer.
- */
- SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
-
- /*
- * Written by the host if the guest requested the host to preempt
- * the command buffer. The device will not raise any IRQs and the
- * command buffer was not processed.
- */
- SVGA_CB_STATUS_PREEMPTED = 5,
-
- /*
- * Written by the host synchronously with the command buffer
- * submission to indicate the the command buffer was not submitted
- * due to an error. No IRQ is raised.
- */
- SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
-
- /*
- * Written by the host when the host finished a
- * SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer
- * queue. The offset of the first byte not processed is stored in
- * the errorOffset field of the command buffer header. All guest
- * visible side effects of commands till that point are guaranteed
- * to be finished before this is written. The
- * SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the
- * SVGA_CB_FLAG_NO_IRQ is not set.
- */
- SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
+
+ SVGA_CB_STATUS_NONE = 0,
+
+ SVGA_CB_STATUS_COMPLETED = 1,
+
+ SVGA_CB_STATUS_QUEUE_FULL = 2,
+
+ SVGA_CB_STATUS_COMMAND_ERROR = 3,
+
+ SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
+
+ SVGA_CB_STATUS_PREEMPTED = 5,
+
+ SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
+
+ SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
} SVGACBStatus;
typedef enum {
- SVGA_CB_FLAG_NONE = 0,
- SVGA_CB_FLAG_NO_IRQ = 1 << 0,
- SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
- SVGA_CB_FLAG_MOB = 1 << 2,
+ SVGA_CB_FLAG_NONE = 0,
+ SVGA_CB_FLAG_NO_IRQ = 1 << 0,
+ SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
+ SVGA_CB_FLAG_MOB = 1 << 2,
} SVGACBFlags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- volatile SVGACBStatus status; /* Modified by device. */
- volatile uint32 errorOffset; /* Modified by device. */
- uint64 id;
- SVGACBFlags flags;
- uint32 length;
- union {
- PA pa;
- struct {
- SVGAMobId mobid;
- uint32 mobOffset;
- } mob;
- } ptr;
- uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
- * modified by device.
- */
- uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
- uint32 mustBeZero[6];
-}
-#include "vmware_pack_end.h"
-SVGACBHeader;
+#pragma pack(push, 1)
+typedef struct {
+ volatile SVGACBStatus status;
+ volatile uint32 errorOffset;
+ uint64 id;
+ SVGACBFlags flags;
+ uint32 length;
+ union {
+ PA pa;
+ struct {
+ SVGAMobId mobid;
+ uint32 mobOffset;
+ } mob;
+ } ptr;
+ uint32 offset;
+ uint32 dxContext;
+ uint32 mustBeZero[6];
+} SVGACBHeader;
+#pragma pack(pop)
typedef enum {
- SVGA_DC_CMD_NOP = 0,
- SVGA_DC_CMD_START_STOP_CONTEXT = 1,
- SVGA_DC_CMD_PREEMPT = 2,
- SVGA_DC_CMD_START_QUEUE = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */
- SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */
- SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */
- SVGA_DC_CMD_MAX = 6,
+ SVGA_DC_CMD_NOP = 0,
+ SVGA_DC_CMD_START_STOP_CONTEXT = 1,
+ SVGA_DC_CMD_PREEMPT = 2,
+ SVGA_DC_CMD_START_QUEUE = 3,
+ SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4,
+ SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5,
+ SVGA_DC_CMD_MAX = 6
} SVGADeviceContextCmdId;
-/*
- * Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1.
- */
-
typedef struct SVGADCCmdStartStop {
- uint32 enable;
- SVGACBContext context; /* Must be zero */
+ uint32 enable;
+ SVGACBContext context;
} SVGADCCmdStartStop;
-/*
- * SVGADCCmdPreempt --
- *
- * This command allows the guest to request that all command buffers
- * on SVGA_CB_CONTEXT_0 be preempted that can be. After execution
- * of this command all command buffers that were preempted will
- * already have SVGA_CB_STATUS_PREEMPTED written into the status
- * field. The device might still be processing a command buffer,
- * assuming execution of it started before the preemption request was
- * received. Specifying the ignoreIDZero flag to TRUE will cause the
- * device to not preempt command buffers with the id field in the
- * command buffer header set to zero.
- */
-
typedef struct SVGADCCmdPreempt {
- SVGACBContext context; /* Must be zero */
- uint32 ignoreIDZero;
+ SVGACBContext context;
+ uint32 ignoreIDZero;
} SVGADCCmdPreempt;
-/*
- * Starts the requested command buffer processing queue. Valid only
- * if the SVGA_CAP_HP_CMD_QUEUE cap is set.
- *
- * For a command queue to be considered runnable it must be enabled
- * and any corresponding higher priority queues must also be enabled.
- * For example in order for command buffers to be processed on
- * SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must
- * be enabled. But for commands to be runnable on SVGA_CB_CONTEXT_1
- * only that queue must be enabled.
- */
-
typedef struct SVGADCCmdStartQueue {
- SVGACBContext context;
+ SVGACBContext context;
} SVGADCCmdStartQueue;
-/*
- * Requests the SVGA device to stop processing the requested command
- * buffer queue as soon as possible. The guest knows the stop has
- * completed when one of the following happens.
- *
- * 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned
- * 2) A command buffer error is encountered with would stop the queue
- * regardless of the async stop request.
- * 3) All command buffers that have been submitted complete successfully.
- * 4) The stop completes synchronously if no command buffers are
- * active on the queue when it is issued.
- *
- * If the command queue is not in a runnable state there is no
- * guarentee this async stop will finish. For instance if the high
- * priority queue is not enabled and a stop is requested on the low
- * priority queue, the high priority queue must be reenabled to
- * guarantee that the async stop will finish.
- *
- * This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used
- * to implement mid command buffer preemption.
- *
- * Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set.
- */
-
typedef struct SVGADCCmdAsyncStopQueue {
- SVGACBContext context;
+ SVGACBContext context;
} SVGADCCmdAsyncStopQueue;
-/*
- * Requests the SVGA device to throw away any full command buffers on
- * the requested command queue that have not been started. For a
- * driver to know which command buffers were thrown away a driver
- * should only issue this command when the queue is stopped, for
- * whatever reason.
- */
-
typedef struct SVGADCCmdEmptyQueue {
- SVGACBContext context;
+ SVGACBContext context;
} SVGADCCmdEmptyQueue;
-
-/*
- * SVGAGMRImageFormat --
- *
- * This is a packed representation of the source 2D image format
- * for a GMR-to-screen blit. Currently it is defined as an encoding
- * of the screen's color depth and bits-per-pixel, however, 16 bits
- * are reserved for future use to identify other encodings (such as
- * RGBA or higher-precision images).
- *
- * Currently supported formats:
- *
- * bpp depth Format Name
- * --- ----- -----------
- * 32 24 32-bit BGRX
- * 24 24 24-bit BGR
- * 16 16 RGB 5-6-5
- * 16 15 RGB 5-5-5
- *
- */
-
typedef struct SVGAGMRImageFormat {
- union {
- struct {
- uint32 bitsPerPixel : 8;
- uint32 colorDepth : 8;
- uint32 reserved : 16; /* Must be zero */
- };
-
- uint32 value;
- };
+ union {
+ struct {
+ uint32 bitsPerPixel : 8;
+ uint32 colorDepth : 8;
+ uint32 reserved : 16;
+ };
+
+ uint32 value;
+ };
} SVGAGMRImageFormat;
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAGuestImage {
- SVGAGuestPtr ptr;
-
- /*
- * A note on interpretation of pitch: This value of pitch is the
- * number of bytes between vertically adjacent image
- * blocks. Normally this is the number of bytes between the first
- * pixel of two adjacent scanlines. With compressed textures,
- * however, this may represent the number of bytes between
- * compression blocks rather than between rows of pixels.
- *
- * XXX: Compressed textures currently must be tightly packed in guest memory.
- *
- * If the image is 1-dimensional, pitch is ignored.
- *
- * If 'pitch' is zero, the SVGA3D device calculates a pitch value
- * assuming each row of blocks is tightly packed.
- */
- uint32 pitch;
-}
-#include "vmware_pack_end.h"
-SVGAGuestImage;
+#pragma pack(push, 1)
+typedef struct SVGAGuestImage {
+ SVGAGuestPtr ptr;
-/*
- * SVGAColorBGRX --
- *
- * A 24-bit color format (BGRX), which does not depend on the
- * format of the legacy guest framebuffer (GFB) or the current
- * GMRFB state.
- */
+ uint32 pitch;
+} SVGAGuestImage;
+#pragma pack(pop)
typedef struct SVGAColorBGRX {
- union {
- struct {
- uint32 b : 8;
- uint32 g : 8;
- uint32 r : 8;
- uint32 x : 8; /* Unused */
- };
-
- uint32 value;
- };
+ union {
+ struct {
+ uint32 b : 8;
+ uint32 g : 8;
+ uint32 r : 8;
+ uint32 x : 8;
+ };
+
+ uint32 value;
+ };
} SVGAColorBGRX;
-
-/*
- * SVGASignedRect --
- * SVGASignedPoint --
- *
- * Signed rectangle and point primitives. These are used by the new
- * 2D primitives for drawing to Screen Objects, which can occupy a
- * signed virtual coordinate space.
- *
- * SVGASignedRect specifies a half-open interval: the (left, top)
- * pixel is part of the rectangle, but the (right, bottom) pixel is
- * not.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- int32 left;
- int32 top;
- int32 right;
- int32 bottom;
-}
-#include "vmware_pack_end.h"
-SVGASignedRect;
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- int32 x;
- int32 y;
-}
-#include "vmware_pack_end.h"
-SVGASignedPoint;
-
-
-/*
- * SVGA Device Capabilities
- *
- * Note the holes in the bitfield. Missing bits have been deprecated,
- * and must not be reused. Those capabilities will never be reported
- * by new versions of the SVGA device.
- *
- * SVGA_CAP_IRQMASK --
- * Provides device interrupts. Adds device register SVGA_REG_IRQMASK
- * to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
- * set/clear pending interrupts.
- *
- * SVGA_CAP_GMR --
- * Provides synchronous mapping of guest memory regions (GMR).
- * Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
- * SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
- *
- * SVGA_CAP_TRACES --
- * Allows framebuffer trace-based updates even when FIFO is enabled.
- * Adds device register SVGA_REG_TRACES.
- *
- * SVGA_CAP_GMR2 --
- * Provides asynchronous commands to define and remap guest memory
- * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
- * SVGA_REG_MEMORY_SIZE.
- *
- * SVGA_CAP_SCREEN_OBJECT_2 --
- * Allow screen object support, and require backing stores from the
- * guest for each screen object.
- *
- * SVGA_CAP_COMMAND_BUFFERS --
- * Enable register based command buffer submission.
- *
- * SVGA_CAP_DEAD1 --
- * This cap was incorrectly used by old drivers and should not be
- * reused.
- *
- * SVGA_CAP_CMD_BUFFERS_2 --
- * Enable support for the prepend command buffer submision
- * registers. SVGA_REG_CMD_PREPEND_LOW and
- * SVGA_REG_CMD_PREPEND_HIGH.
- *
- * SVGA_CAP_GBOBJECTS --
- * Enable guest-backed objects and surfaces.
- *
- * SVGA_CAP_DX --
- * Enable support for DX commands, and command buffers in a mob.
- *
- * SVGA_CAP_HP_CMD_QUEUE --
- * Enable support for the high priority command queue, and the
- * ScreenCopy command.
- *
- * SVGA_CAP_NO_BB_RESTRICTION --
- * Allow ScreenTargets to be defined without regard to the 32-bpp
- * bounding-box memory restrictions. ie:
- *
- * The summed memory usage of all screens (assuming they were defined as
- * 32-bpp) must always be less than the value of the
- * SVGA_REG_MAX_PRIMARY_MEM register.
- *
- * If this cap is not present, the 32-bpp bounding box around all screens
- * must additionally be under the value of the SVGA_REG_MAX_PRIMARY_MEM
- * register.
- *
- * If the cap is present, the bounding box restriction is lifted (and only
- * the screen-sum limit applies).
- *
- * (Note that this is a slight lie... there is still a sanity limit on any
- * dimension of the topology to be less than SVGA_SCREEN_ROOT_LIMIT, even
- * when SVGA_CAP_NO_BB_RESTRICTION is present, but that should be
- * large enough to express any possible topology without holes between
- * monitors.)
- *
- * SVGA_CAP_CAP2_REGISTER --
- * If this cap is present, the SVGA_REG_CAP2 register is supported.
- */
-
-#define SVGA_CAP_NONE 0x00000000
-#define SVGA_CAP_RECT_COPY 0x00000002
-#define SVGA_CAP_CURSOR 0x00000020
-#define SVGA_CAP_CURSOR_BYPASS 0x00000040
-#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
-#define SVGA_CAP_8BIT_EMULATION 0x00000100
-#define SVGA_CAP_ALPHA_CURSOR 0x00000200
-#define SVGA_CAP_3D 0x00004000
-#define SVGA_CAP_EXTENDED_FIFO 0x00008000
-#define SVGA_CAP_MULTIMON 0x00010000
-#define SVGA_CAP_PITCHLOCK 0x00020000
-#define SVGA_CAP_IRQMASK 0x00040000
-#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
-#define SVGA_CAP_GMR 0x00100000
-#define SVGA_CAP_TRACES 0x00200000
-#define SVGA_CAP_GMR2 0x00400000
-#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
-#define SVGA_CAP_COMMAND_BUFFERS 0x01000000
-#define SVGA_CAP_DEAD1 0x02000000
-#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
-#define SVGA_CAP_GBOBJECTS 0x08000000
-#define SVGA_CAP_DX 0x10000000
-#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
-#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
-#define SVGA_CAP_CAP2_REGISTER 0x80000000
-
-/*
- * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
- *
- * SVGA_CAP2_GROW_OTABLE --
- * Allow the GrowOTable/DXGrowCOTable commands.
- *
- * SVGA_CAP2_INTRA_SURFACE_COPY --
- * Allow the IntraSurfaceCopy command.
- *
- * SVGA_CAP2_DX2 --
- * Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
- * HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register.
- *
- * SVGA_CAP2_GB_MEMSIZE_2 --
- * Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register.
- *
- * SVGA_CAP2_SCREENDMA_REG --
- * Allow the SVGA_REG_SCREENDMA register.
- *
- * SVGA_CAP2_OTABLE_PTDEPTH_2 --
- * Allow 2 level page tables for OTable commands.
- *
- * SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT --
- * Allow a stretch blt from a non-multisampled surface to a multisampled
- * surface.
- *
- * SVGA_CAP2_CURSOR_MOB --
- * Allow the SVGA_REG_CURSOR_MOBID register.
- *
- * SVGA_CAP2_MSHINT --
- * Allow the SVGA_REG_MSHINT register.
- *
- * SVGA_CAP2_DX3 --
- * Allows the DefineGBSurface_v4 command.
- * Allows the DXDefineDepthStencilView_v2, DXDefineStreamOutputWithMob,
- * and DXBindStreamOutput commands if 3D is also available.
- * Allows the DXPredStagingCopy and DXStagingCopy commands if SM41
- * is also available.
- *
- * SVGA_CAP2_RESERVED --
- * Reserve the last bit for extending the SVGA capabilities to some
- * future mechanisms.
- */
-#define SVGA_CAP2_NONE 0x00000000
-#define SVGA_CAP2_GROW_OTABLE 0x00000001
-#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
-#define SVGA_CAP2_DX2 0x00000004
-#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
-#define SVGA_CAP2_SCREENDMA_REG 0x00000010
-#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
+#pragma pack(push, 1)
+typedef struct {
+ int32 left;
+ int32 top;
+ int32 right;
+ int32 bottom;
+} SVGASignedRect;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ int32 x;
+ int32 y;
+} SVGASignedPoint;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 x;
+ uint32 y;
+} SVGAUnsignedPoint;
+#pragma pack(pop)
+
+#define SVGA_CAP_NONE 0x00000000
+#define SVGA_CAP_RECT_COPY 0x00000002
+#define SVGA_CAP_CURSOR 0x00000020
+#define SVGA_CAP_CURSOR_BYPASS 0x00000040
+#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
+#define SVGA_CAP_8BIT_EMULATION 0x00000100
+#define SVGA_CAP_ALPHA_CURSOR 0x00000200
+#define SVGA_CAP_3D 0x00004000
+#define SVGA_CAP_EXTENDED_FIFO 0x00008000
+#define SVGA_CAP_MULTIMON 0x00010000
+#define SVGA_CAP_PITCHLOCK 0x00020000
+#define SVGA_CAP_IRQMASK 0x00040000
+#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
+#define SVGA_CAP_GMR 0x00100000
+#define SVGA_CAP_TRACES 0x00200000
+#define SVGA_CAP_GMR2 0x00400000
+#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
+#define SVGA_CAP_COMMAND_BUFFERS 0x01000000
+#define SVGA_CAP_DEAD1 0x02000000
+#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
+#define SVGA_CAP_GBOBJECTS 0x08000000
+#define SVGA_CAP_DX 0x10000000
+#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
+#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
+#define SVGA_CAP_CAP2_REGISTER 0x80000000
+
+#define SVGA_CAP2_NONE 0x00000000
+#define SVGA_CAP2_GROW_OTABLE 0x00000001
+#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
+#define SVGA_CAP2_DX2 0x00000004
+#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
+#define SVGA_CAP2_SCREENDMA_REG 0x00000010
+#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040
-#define SVGA_CAP2_CURSOR_MOB 0x00000080
-#define SVGA_CAP2_MSHINT 0x00000100
-#define SVGA_CAP2_DX3 0x00000400
-#define SVGA_CAP2_RESERVED 0x80000000
-
-
-/*
- * The Guest can optionally read some SVGA device capabilities through
- * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
- * the SVGA device is initialized. The type of capability the guest
- * is requesting from the SVGABackdoorCapType enum should be placed in
- * the upper 16 bits of the backdoor command id (ECX). On success the
- * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
- * the requested capability. If the command is not supported then EBX
- * will be left unchanged and EAX will be set to -1. Because it is
- * possible that -1 is the value of the requested cap the correct way
- * to check if the command was successful is to check if EBX was changed
- * to BDOOR_MAGIC making sure to initialize the register to something
- * else first.
- */
+#define SVGA_CAP2_CURSOR_MOB 0x00000080
+#define SVGA_CAP2_MSHINT 0x00000100
+#define SVGA_CAP2_CB_MAX_SIZE_4MB 0x00000200
+#define SVGA_CAP2_DX3 0x00000400
+#define SVGA_CAP2_FRAME_TYPE 0x00000800
+#define SVGA_CAP2_COTABLE_COPY 0x00001000
+#define SVGA_CAP2_TRACE_FULL_FB 0x00002000
+#define SVGA_CAP2_EXTRA_REGS 0x00004000
+#define SVGA_CAP2_LO_STAGING 0x00008000
+#define SVGA_CAP2_RESERVED 0x80000000
typedef enum {
- SVGABackdoorCapDeviceCaps = 0,
- SVGABackdoorCapFifoCaps = 1,
- SVGABackdoorCap3dHWVersion = 2,
- SVGABackdoorCapDeviceCaps2 = 3,
- SVGABackdoorCapDevelCaps = 4,
- SVGABackdoorDevelRenderer = 5,
- SVGABackdoorCapMax = 6,
+ SVGABackdoorCapDeviceCaps = 0,
+ SVGABackdoorCapFifoCaps = 1,
+ SVGABackdoorCap3dHWVersion = 2,
+ SVGABackdoorCapDeviceCaps2 = 3,
+ SVGABackdoorCapDevelCaps = 4,
+ SVGABackdoorDevelRenderer = 5,
+ SVGABackdoorDevelUsingISB = 6,
+ SVGABackdoorCapMax = 7,
} SVGABackdoorCapType;
-
-/*
- * FIFO register indices.
- *
- * The FIFO is a chunk of device memory mapped into guest physmem. It
- * is always treated as 32-bit words.
- *
- * The guest driver gets to decide how to partition it between
- * - FIFO registers (there are always at least 4, specifying where the
- * following data area is and how much data it contains; there may be
- * more registers following these, depending on the FIFO protocol
- * version in use)
- * - FIFO data, written by the guest and slurped out by the VMX.
- * These indices are 32-bit word offsets into the FIFO.
- */
-
enum {
- /*
- * Block 1 (basic registers): The originally defined FIFO registers.
- * These exist and are valid for all versions of the FIFO protocol.
- */
-
- SVGA_FIFO_MIN = 0,
- SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
- SVGA_FIFO_NEXT_CMD,
- SVGA_FIFO_STOP,
-
- /*
- * Block 2 (extended registers): Mandatory registers for the extended
- * FIFO. These exist if the SVGA caps register includes
- * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
- * associated capability bit is enabled.
- *
- * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
- * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
- * This means that the guest has to test individually (in most cases
- * using FIFO caps) for the presence of registers after this; the VMX
- * can define "extended FIFO" to mean whatever it wants, and currently
- * won't enable it unless there's room for that set and much more.
- */
-
- SVGA_FIFO_CAPABILITIES = 4,
- SVGA_FIFO_FLAGS,
- /* Valid with SVGA_FIFO_CAP_FENCE: */
- SVGA_FIFO_FENCE,
-
- /*
- * Block 3a (optional extended registers): Additional registers for the
- * extended FIFO, whose presence isn't actually implied by
- * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
- * leave room for them.
- *
- * These in block 3a, the VMX currently considers mandatory for the
- * extended FIFO.
- */
-
- /* Valid if exists (i.e. if extended FIFO enabled): */
- SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */
- /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
- SVGA_FIFO_PITCHLOCK,
-
- /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
- SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */
- SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */
- SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */
- SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */
- SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
-
- /* Valid with SVGA_FIFO_CAP_RESERVE: */
- SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */
-
- /*
- * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
- *
- * By default this is SVGA_ID_INVALID, to indicate that the cursor
- * coordinates are specified relative to the virtual root. If this
- * is set to a specific screen ID, cursor position is reinterpreted
- * as a signed offset relative to that screen's origin.
- */
- SVGA_FIFO_CURSOR_SCREEN_ID,
-
- /*
- * Valid with SVGA_FIFO_CAP_DEAD
- *
- * An arbitrary value written by the host, drivers should not use it.
- */
- SVGA_FIFO_DEAD,
-
- /*
- * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
- *
- * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
- * on platforms that can enforce graphics resource limits.
- */
- SVGA_FIFO_3D_HWVERSION_REVISED,
-
- /*
- * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
- * registers, but this must be done carefully and with judicious use of
- * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
- * enough to tell you whether the register exists: we've shipped drivers
- * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
- * the earlier ones. The actual order of introduction was:
- * - PITCHLOCK
- * - 3D_CAPS
- * - CURSOR_* (cursor bypass 3)
- * - RESERVED
- * So, code that wants to know whether it can use any of the
- * aforementioned registers, or anything else added after PITCHLOCK and
- * before 3D_CAPS, needs to reason about something other than
- * SVGA_FIFO_MIN.
- */
-
- /*
- * 3D caps block space; valid with 3D hardware version >=
- * SVGA3D_HWVERSION_WS6_B1.
- */
- SVGA_FIFO_3D_CAPS = 32,
- SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
-
- /*
- * End of VMX's current definition of "extended-FIFO registers".
- * Registers before here are always enabled/disabled as a block; either
- * the extended FIFO is enabled and includes all preceding registers, or
- * it's disabled entirely.
- *
- * Block 3b (truly optional extended registers): Additional registers for
- * the extended FIFO, which the VMX already knows how to enable and
- * disable with correct granularity.
- *
- * Registers after here exist if and only if the guest SVGA driver
- * sets SVGA_FIFO_MIN high enough to leave room for them.
- */
-
- /* Valid if register exists: */
- SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
- SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
- SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */
-
- /*
- * Always keep this last. This defines the maximum number of
- * registers we know about. At power-on, this value is placed in
- * the SVGA_REG_MEM_REGS register, and we expect the guest driver
- * to allocate this much space in FIFO memory for registers.
- */
- SVGA_FIFO_NUM_REGS
-};
+ SVGA_FIFO_MIN = 0,
+ SVGA_FIFO_MAX,
+ SVGA_FIFO_NEXT_CMD,
+ SVGA_FIFO_STOP,
-/*
- * Definition of registers included in extended FIFO support.
- *
- * The guest SVGA driver gets to allocate the FIFO between registers
- * and data. It must always allocate at least 4 registers, but old
- * drivers stopped there.
- *
- * The VMX will enable extended FIFO support if and only if the guest
- * left enough room for all registers defined as part of the mandatory
- * set for the extended FIFO.
- *
- * Note that the guest drivers typically allocate the FIFO only at
- * initialization time, not at mode switches, so it's likely that the
- * number of FIFO registers won't change without a reboot.
- *
- * All registers less than this value are guaranteed to be present if
- * svgaUser->fifo.extended is set. Any later registers must be tested
- * individually for compatibility at each use (in the VMX).
- *
- * This value is used only by the VMX, so it can change without
- * affecting driver compatibility; keep it that way?
- */
-#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
+ SVGA_FIFO_CAPABILITIES = 4,
+ SVGA_FIFO_FLAGS,
+ SVGA_FIFO_FENCE,
-/*
- * FIFO Synchronization Registers
- *
- * SVGA_REG_SYNC --
- *
- * The SYNC register can be used by the guest driver to signal to the
- * device that the guest driver is waiting for previously submitted
- * commands to complete.
- *
- * When the guest driver writes to the SYNC register, the device sets
- * the BUSY register to TRUE, and starts processing the submitted commands
- * (if it was not already doing so). When all previously submitted
- * commands are finished and the device is idle again, it sets the BUSY
- * register back to FALSE. (If the guest driver submits new commands
- * after writing the SYNC register, the new commands are not guaranteed
- * to have been procesesd.)
- *
- * When guest drivers are submitting commands using the FIFO, the device
- * periodically polls to check for new FIFO commands when idle, which may
- * introduce a delay in command processing. If the guest-driver wants
- * the commands to be processed quickly (which it typically does), it
- * should write SYNC after each batch of commands is committed to the
- * FIFO to immediately wake up the device. For even better performance,
- * the guest can use the SVGA_FIFO_BUSY register to avoid these extra
- * SYNC writes if the device is already active, using the technique known
- * as "Ringing the Doorbell" (described below). (Note that command
- * buffer submission implicitly wakes up the device, and so doesn't
- * suffer from this problem.)
- *
- * The SYNC register can also be used in combination with BUSY to
- * synchronously ensure that all SVGA commands are processed (with both
- * the FIFO and command-buffers). To do this, the guest driver should
- * write to SYNC, and then loop reading BUSY until BUSY returns FALSE.
- * This technique is known as a "Legacy Sync".
- *
- * SVGA_REG_BUSY --
- *
- * This register is set to TRUE when SVGA_REG_SYNC is written,
- * and is set back to FALSE when the device has finished processing
- * all commands and is idle again.
- *
- * Every read from the BUSY reigster will block for an undefined
- * amount of time (normally until the device finishes some interesting
- * work unit), or the device is idle.
- *
- * Guest drivers can also do a partial Legacy Sync to check for some
- * particular condition, for instance by stopping early when a fence
- * passes before BUSY has been set back to FALSE. This is particularly
- * useful if the guest-driver knows that it is blocked waiting on the
- * device, because it will yield CPU time back to the host.
- *
- * SVGA_FIFO_BUSY --
- *
- * The SVGA_FIFO_BUSY register is a fast way for the guest driver to check
- * whether the device is actively processing FIFO commands before writing
- * the more expensive SYNC register.
- *
- * If this register reads as TRUE, the device is actively processing
- * FIFO commands.
- *
- * If this register reads as FALSE, the device may not be actively
- * processing commands, and the guest driver should try
- * "Ringing the Doorbell".
- *
- * To Ring the Doorbell, the guest should:
- *
- * 1. Have already written their batch of commands into the FIFO.
- * 2. Check if the SVGA_FIFO_BUSY register is available by reading
- * SVGA_FIFO_MIN.
- * 3. Read SVGA_FIFO_BUSY. If it reads as TRUE, the device is actively
- * processing FIFO commands, and no further action is necessary.
- * 4. If SVGA_FIFO_BUSY was FALSE, write TRUE to SVGA_REG_SYNC.
- *
- * For maximum performance, this procedure should be followed after
- * every meaningful batch of commands has been written into the FIFO.
- * (Normally when the underlying application signals it's finished a
- * meaningful work unit by calling Flush.)
- */
+ SVGA_FIFO_3D_HWVERSION,
+ SVGA_FIFO_PITCHLOCK,
-/*
- * FIFO Capabilities
- *
- * Fence -- Fence register and command are supported
- * Accel Front -- Front buffer only commands are supported
- * Pitch Lock -- Pitch lock register is supported
- * Video -- SVGA Video overlay units are supported
- * Escape -- Escape command is supported
- *
- * SVGA_FIFO_CAP_SCREEN_OBJECT --
- *
- * Provides dynamic multi-screen rendering, for improved Unity and
- * multi-monitor modes. With Screen Object, the guest can
- * dynamically create and destroy 'screens', which can represent
- * Unity windows or virtual monitors. Screen Object also provides
- * strong guarantees that DMA operations happen only when
- * guest-initiated. Screen Object deprecates the BAR1 guest
- * framebuffer (GFB) and all commands that work only with the GFB.
- *
- * New registers:
- * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
- *
- * New 2D commands:
- * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
- * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
- *
- * New 3D commands:
- * BLIT_SURFACE_TO_SCREEN
- *
- * New guarantees:
- *
- * - The host will not read or write guest memory, including the GFB,
- * except when explicitly initiated by a DMA command.
- *
- * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
- * is guaranteed to complete before any subsequent FENCEs.
- *
- * - All legacy commands which affect a Screen (UPDATE, PRESENT,
- * PRESENT_READBACK) as well as new Screen blit commands will
- * all behave consistently as blits, and memory will be read
- * or written in FIFO order.
- *
- * For example, if you PRESENT from one SVGA3D surface to multiple
- * places on the screen, the data copied will always be from the
- * SVGA3D surface at the time the PRESENT was issued in the FIFO.
- * This was not necessarily true on devices without Screen Object.
- *
- * This means that on devices that support Screen Object, the
- * PRESENT_READBACK command should not be necessary unless you
- * actually want to read back the results of 3D rendering into
- * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
- * command provides a strict superset of functionality.)
- *
- * - When a screen is resized, either using Screen Object commands or
- * legacy multimon registers, its contents are preserved.
- *
- * SVGA_FIFO_CAP_GMR2 --
- *
- * Provides new commands to define and remap guest memory regions (GMR).
- *
- * New 2D commands:
- * DEFINE_GMR2, REMAP_GMR2.
- *
- * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
- *
- * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
- * This register may replace SVGA_FIFO_3D_HWVERSION on platforms
- * that enforce graphics resource limits. This allows the platform
- * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
- * drivers that do not limit their resources.
- *
- * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
- * are codependent (and thus we use a single capability bit).
- *
- * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
- *
- * Modifies the DEFINE_SCREEN command to include a guest provided
- * backing store in GMR memory and the bytesPerLine for the backing
- * store. This capability requires the use of a backing store when
- * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
- * is present then backing stores are optional.
- *
- * SVGA_FIFO_CAP_DEAD --
- *
- * Drivers should not use this cap bit. This cap bit can not be
- * reused since some hosts already expose it.
- */
+ SVGA_FIFO_CURSOR_ON,
+ SVGA_FIFO_CURSOR_X,
+ SVGA_FIFO_CURSOR_Y,
+ SVGA_FIFO_CURSOR_COUNT,
+ SVGA_FIFO_CURSOR_LAST_UPDATED,
-#define SVGA_FIFO_CAP_NONE 0
-#define SVGA_FIFO_CAP_FENCE (1<<0)
-#define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
-#define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
-#define SVGA_FIFO_CAP_VIDEO (1<<3)
-#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4)
-#define SVGA_FIFO_CAP_ESCAPE (1<<5)
-#define SVGA_FIFO_CAP_RESERVE (1<<6)
-#define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7)
-#define SVGA_FIFO_CAP_GMR2 (1<<8)
-#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
-#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9)
-#define SVGA_FIFO_CAP_DEAD (1<<10)
+ SVGA_FIFO_RESERVED,
+ SVGA_FIFO_CURSOR_SCREEN_ID,
-/*
- * FIFO Flags
- *
- * Accel Front -- Driver should use front buffer only commands
- */
+ SVGA_FIFO_DEAD,
-#define SVGA_FIFO_FLAG_NONE 0
-#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
-#define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */
+ SVGA_FIFO_3D_HWVERSION_REVISED,
-/*
- * FIFO reservation sentinel value
- */
+ SVGA_FIFO_3D_CAPS = 32,
+ SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
-#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
+ SVGA_FIFO_GUEST_3D_HWVERSION,
+ SVGA_FIFO_FENCE_GOAL,
+ SVGA_FIFO_BUSY,
+ SVGA_FIFO_NUM_REGS
+};
-/*
- * ScreenDMA Register Values
- */
+#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1)
-#define SVGA_SCREENDMA_REG_UNDEFINED 0
-#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
-#define SVGA_SCREENDMA_REG_PRESENT 2
-#define SVGA_SCREENDMA_REG_MAX 3
+#define SVGA3D_FIFO_CAPS_RECORD_DEVCAPS 0x100
+typedef uint32 SVGA3dFifoCapsRecordType;
-/*
- * Video overlay support
- */
+typedef uint32 SVGA3dFifoCapPair[2];
-#define SVGA_NUM_OVERLAY_UNITS 32
+#pragma pack(push, 1)
+typedef struct SVGA3dFifoCapsRecordHeader {
+ uint32 length;
+ SVGA3dFifoCapsRecordType type;
+} SVGA3dFifoCapsRecordHeader;
+#pragma pack(pop)
-/*
- * Video capabilities that the guest is currently using
- */
+#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
-#define SVGA_VIDEO_FLAG_COLORKEY 0x0001
+#define SVGA_FIFO_CAP_NONE 0
+#define SVGA_FIFO_CAP_FENCE (1 << 0)
+#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
+#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
+#define SVGA_FIFO_CAP_VIDEO (1 << 3)
+#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1 << 4)
+#define SVGA_FIFO_CAP_ESCAPE (1 << 5)
+#define SVGA_FIFO_CAP_RESERVE (1 << 6)
+#define SVGA_FIFO_CAP_SCREEN_OBJECT (1 << 7)
+#define SVGA_FIFO_CAP_GMR2 (1 << 8)
+#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
+#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1 << 9)
+#define SVGA_FIFO_CAP_DEAD (1 << 10)
+#define SVGA_FIFO_FLAG_NONE 0
+#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
+#define SVGA_FIFO_FLAG_RESERVED (1 << 31)
-/*
- * Offsets for the video overlay registers
- */
+#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
-enum {
- SVGA_VIDEO_ENABLED = 0,
- SVGA_VIDEO_FLAGS,
- SVGA_VIDEO_DATA_OFFSET,
- SVGA_VIDEO_FORMAT,
- SVGA_VIDEO_COLORKEY,
- SVGA_VIDEO_SIZE, /* Deprecated */
- SVGA_VIDEO_WIDTH,
- SVGA_VIDEO_HEIGHT,
- SVGA_VIDEO_SRC_X,
- SVGA_VIDEO_SRC_Y,
- SVGA_VIDEO_SRC_WIDTH,
- SVGA_VIDEO_SRC_HEIGHT,
- SVGA_VIDEO_DST_X, /* Signed int32 */
- SVGA_VIDEO_DST_Y, /* Signed int32 */
- SVGA_VIDEO_DST_WIDTH,
- SVGA_VIDEO_DST_HEIGHT,
- SVGA_VIDEO_PITCH_1,
- SVGA_VIDEO_PITCH_2,
- SVGA_VIDEO_PITCH_3,
- SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
- SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
- /* (SVGA_ID_INVALID) */
- SVGA_VIDEO_NUM_REGS
-};
+#define SVGA_SCREENDMA_REG_UNDEFINED 0
+#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
+#define SVGA_SCREENDMA_REG_PRESENT 2
+#define SVGA_SCREENDMA_REG_MAX 3
+#define SVGA_NUM_OVERLAY_UNITS 32
-/*
- * SVGA Overlay Units
- *
- * width and height relate to the entire source video frame.
- * srcX, srcY, srcWidth and srcHeight represent subset of the source
- * video frame to be displayed.
- */
+#define SVGA_VIDEO_FLAG_COLORKEY 0x0001
-typedef
-#include "vmware_pack_begin.h"
-struct SVGAOverlayUnit {
- uint32 enabled;
- uint32 flags;
- uint32 dataOffset;
- uint32 format;
- uint32 colorKey;
- uint32 size;
- uint32 width;
- uint32 height;
- uint32 srcX;
- uint32 srcY;
- uint32 srcWidth;
- uint32 srcHeight;
- int32 dstX;
- int32 dstY;
- uint32 dstWidth;
- uint32 dstHeight;
- uint32 pitches[3];
- uint32 dataGMRId;
- uint32 dstScreenId;
-}
-#include "vmware_pack_end.h"
-SVGAOverlayUnit;
+enum {
+ SVGA_VIDEO_ENABLED = 0,
+ SVGA_VIDEO_FLAGS,
+ SVGA_VIDEO_DATA_OFFSET,
+ SVGA_VIDEO_FORMAT,
+ SVGA_VIDEO_COLORKEY,
+ SVGA_VIDEO_SIZE,
+ SVGA_VIDEO_WIDTH,
+ SVGA_VIDEO_HEIGHT,
+ SVGA_VIDEO_SRC_X,
+ SVGA_VIDEO_SRC_Y,
+ SVGA_VIDEO_SRC_WIDTH,
+ SVGA_VIDEO_SRC_HEIGHT,
+ SVGA_VIDEO_DST_X,
+ SVGA_VIDEO_DST_Y,
+ SVGA_VIDEO_DST_WIDTH,
+ SVGA_VIDEO_DST_HEIGHT,
+ SVGA_VIDEO_PITCH_1,
+ SVGA_VIDEO_PITCH_2,
+ SVGA_VIDEO_PITCH_3,
+ SVGA_VIDEO_DATA_GMRID,
+ SVGA_VIDEO_DST_SCREEN_ID,
+ SVGA_VIDEO_NUM_REGS
+};
+#pragma pack(push, 1)
+typedef struct SVGAOverlayUnit {
+ uint32 enabled;
+ uint32 flags;
+ uint32 dataOffset;
+ uint32 format;
+ uint32 colorKey;
+ uint32 size;
+ uint32 width;
+ uint32 height;
+ uint32 srcX;
+ uint32 srcY;
+ uint32 srcWidth;
+ uint32 srcHeight;
+ int32 dstX;
+ int32 dstY;
+ uint32 dstWidth;
+ uint32 dstHeight;
+ uint32 pitches[3];
+ uint32 dataGMRId;
+ uint32 dstScreenId;
+} SVGAOverlayUnit;
+#pragma pack(pop)
-/*
- * Guest display topology
- *
- * XXX: This structure is not part of the SVGA device's interface, and
- * doesn't really belong here.
- */
#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
typedef struct SVGADisplayTopology {
- uint16 displayId;
- uint16 isPrimary;
- uint32 width;
- uint32 height;
- uint32 positionX;
- uint32 positionY;
+ uint16 displayId;
+ uint16 isPrimary;
+ uint32 width;
+ uint32 height;
+ uint32 positionX;
+ uint32 positionY;
} SVGADisplayTopology;
-
-/*
- * SVGAScreenObject --
- *
- * This is a new way to represent a guest's multi-monitor screen or
- * Unity window. Screen objects are only supported if the
- * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
- *
- * If Screen Objects are supported, they can be used to fully
- * replace the functionality provided by the framebuffer registers
- * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
- *
- * The screen object is a struct with guaranteed binary
- * compatibility. New flags can be added, and the struct may grow,
- * but existing fields must retain their meaning.
- *
- * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
- * a SVGAGuestPtr that is used to back the screen contents. This
- * memory must come from the GFB. The guest is not allowed to
- * access the memory and doing so will have undefined results. The
- * backing store is required to be page aligned and the size is
- * padded to the next page boundry. The number of pages is:
- * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
- *
- * The pitch in the backingStore is required to be at least large
- * enough to hold a 32bbp scanline. It is recommended that the
- * driver pad bytesPerLine for a potential performance win.
- *
- * The cloneCount field is treated as a hint from the guest that
- * the user wants this display to be cloned, countCount times. A
- * value of zero means no cloning should happen.
- */
-
-#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
-#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
-#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
+#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
+#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET
+#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
-/*
- * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
- * deactivated the base layer is defined to lose all contents and
- * become black. When a screen is deactivated the backing store is
- * optional. When set backingPtr and bytesPerLine will be ignored.
- */
-#define SVGA_SCREEN_DEACTIVATE (1 << 3)
+#define SVGA_SCREEN_DEACTIVATE (1 << 3)
-/*
- * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
- * the screen contents will be outputted as all black to the user
- * though the base layer contents is preserved. The screen base layer
- * can still be read and written to like normal though the no visible
- * effect will be seen by the user. When the flag is changed the
- * screen will be blanked or redrawn to the current contents as needed
- * without any extra commands from the driver. This flag only has an
- * effect when the screen is not deactivated.
- */
#define SVGA_SCREEN_BLANKING (1 << 4)
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 structSize; /* sizeof(SVGAScreenObject) */
- uint32 id;
- uint32 flags;
- struct {
- uint32 width;
- uint32 height;
- } size;
- struct {
- int32 x;
- int32 y;
- } root;
-
- /*
- * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
- * with SVGA_FIFO_CAP_SCREEN_OBJECT.
- */
- SVGAGuestImage backingStore;
-
- /*
- * The cloneCount field is treated as a hint from the guest that
- * the user wants this display to be cloned, cloneCount times.
- *
- * A value of zero means no cloning should happen.
- */
- uint32 cloneCount;
-}
-#include "vmware_pack_end.h"
-SVGAScreenObject;
-
-
-/*
- * Commands in the command FIFO:
- *
- * Command IDs defined below are used for the traditional 2D FIFO
- * communication (not all commands are available for all versions of the
- * SVGA FIFO protocol).
- *
- * Note the holes in the command ID numbers: These commands have been
- * deprecated, and the old IDs must not be reused.
- *
- * Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
- * protocol.
- *
- * Each command's parameters are described by the comments and
- * structs below.
- */
+#pragma pack(push, 1)
+typedef struct {
+ uint32 structSize;
+ uint32 id;
+ uint32 flags;
+ struct {
+ uint32 width;
+ uint32 height;
+ } size;
+ struct {
+ int32 x;
+ int32 y;
+ } root;
+
+ SVGAGuestImage backingStore;
+
+ uint32 cloneCount;
+} SVGAScreenObject;
+#pragma pack(pop)
typedef enum {
- SVGA_CMD_INVALID_CMD = 0,
- SVGA_CMD_UPDATE = 1,
- SVGA_CMD_RECT_COPY = 3,
- SVGA_CMD_RECT_ROP_COPY = 14,
- SVGA_CMD_DEFINE_CURSOR = 19,
- SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
- SVGA_CMD_UPDATE_VERBOSE = 25,
- SVGA_CMD_FRONT_ROP_FILL = 29,
- SVGA_CMD_FENCE = 30,
- SVGA_CMD_ESCAPE = 33,
- SVGA_CMD_DEFINE_SCREEN = 34,
- SVGA_CMD_DESTROY_SCREEN = 35,
- SVGA_CMD_DEFINE_GMRFB = 36,
- SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
- SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
- SVGA_CMD_ANNOTATION_FILL = 39,
- SVGA_CMD_ANNOTATION_COPY = 40,
- SVGA_CMD_DEFINE_GMR2 = 41,
- SVGA_CMD_REMAP_GMR2 = 42,
- SVGA_CMD_DEAD = 43,
- SVGA_CMD_DEAD_2 = 44,
- SVGA_CMD_NOP = 45,
- SVGA_CMD_NOP_ERROR = 46,
- SVGA_CMD_MAX
+ SVGA_CMD_INVALID_CMD = 0,
+ SVGA_CMD_UPDATE = 1,
+ SVGA_CMD_RECT_COPY = 3,
+ SVGA_CMD_RECT_ROP_COPY = 14,
+ SVGA_CMD_DEFINE_CURSOR = 19,
+ SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
+ SVGA_CMD_UPDATE_VERBOSE = 25,
+ SVGA_CMD_FRONT_ROP_FILL = 29,
+ SVGA_CMD_FENCE = 30,
+ SVGA_CMD_ESCAPE = 33,
+ SVGA_CMD_DEFINE_SCREEN = 34,
+ SVGA_CMD_DESTROY_SCREEN = 35,
+ SVGA_CMD_DEFINE_GMRFB = 36,
+ SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
+ SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
+ SVGA_CMD_ANNOTATION_FILL = 39,
+ SVGA_CMD_ANNOTATION_COPY = 40,
+ SVGA_CMD_DEFINE_GMR2 = 41,
+ SVGA_CMD_REMAP_GMR2 = 42,
+ SVGA_CMD_DEAD = 43,
+ SVGA_CMD_DEAD_2 = 44,
+ SVGA_CMD_NOP = 45,
+ SVGA_CMD_NOP_ERROR = 46,
+ SVGA_CMD_MAX
} SVGAFifoCmdId;
-#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
-#define SVGA_CMD_MAX_ARGS 64
-
-
-/*
- * SVGA_CMD_UPDATE --
- *
- * This is a DMA transfer which copies from the Guest Framebuffer
- * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
- * intersect with the provided virtual rectangle.
- *
- * This command does not support using arbitrary guest memory as a
- * data source- it only works with the pre-defined GFB memory.
- * This command also does not support signed virtual coordinates.
- * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
- * negative root x/y coordinates, the negative portion of those
- * screens will not be reachable by this command.
- *
- * This command is not necessary when using framebuffer
- * traces. Traces are automatically enabled if the SVGA FIFO is
- * disabled, and you may explicitly enable/disable traces using
- * SVGA_REG_TRACES. With traces enabled, any write to the GFB will
- * automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
- *
- * Traces and SVGA_CMD_UPDATE are the only supported ways to render
- * pseudocolor screen updates. The newer Screen Object commands
- * only support true color formats.
- *
- * Availability:
- * Always available.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 x;
- uint32 y;
- uint32 width;
- uint32 height;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdUpdate;
-
-
-/*
- * SVGA_CMD_RECT_COPY --
- *
- * Perform a rectangular DMA transfer from one area of the GFB to
- * another, and copy the result to any screens which intersect it.
- *
- * Availability:
- * SVGA_CAP_RECT_COPY
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 srcX;
- uint32 srcY;
- uint32 destX;
- uint32 destY;
- uint32 width;
- uint32 height;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdRectCopy;
-
-
-/*
- * SVGA_CMD_RECT_ROP_COPY --
- *
- * Perform a rectangular DMA transfer from one area of the GFB to
- * another, and copy the result to any screens which intersect it.
- * The value of ROP may only be SVGA_ROP_COPY, and this command is
- * only supported for backwards compatibility reasons.
- *
- * Availability:
- * SVGA_CAP_RECT_COPY
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 srcX;
- uint32 srcY;
- uint32 destX;
- uint32 destY;
- uint32 width;
- uint32 height;
- uint32 rop;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdRectRopCopy;
-
-
-/*
- * SVGA_CMD_DEFINE_CURSOR --
- *
- * Provide a new cursor image, as an AND/XOR mask.
- *
- * The recommended way to position the cursor overlay is by using
- * the SVGA_FIFO_CURSOR_* registers, supported by the
- * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
- *
- * Availability:
- * SVGA_CAP_CURSOR
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 id; /* Reserved, must be zero. */
- uint32 hotspotX;
- uint32 hotspotY;
- uint32 width;
- uint32 height;
- uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
- uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
- /*
- * Followed by scanline data for AND mask, then XOR mask.
- * Each scanline is padded to a 32-bit boundary.
- */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDefineCursor;
-
-
-/*
- * SVGA_CMD_DEFINE_ALPHA_CURSOR --
- *
- * Provide a new cursor image, in 32-bit BGRA format.
- *
- * The recommended way to position the cursor overlay is by using
- * the SVGA_FIFO_CURSOR_* registers, supported by the
- * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
- *
- * Availability:
- * SVGA_CAP_ALPHA_CURSOR
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 id; /* Reserved, must be zero. */
- uint32 hotspotX;
- uint32 hotspotY;
- uint32 width;
- uint32 height;
- /* Followed by scanline data */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDefineAlphaCursor;
-
-
-/*
- * Provide a new large cursor image, as an AND/XOR mask.
- *
- * Should only be used for CursorMob functionality
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 hotspotX;
- uint32 hotspotY;
- uint32 width;
- uint32 height;
- uint32 andMaskDepth;
- uint32 xorMaskDepth;
- /*
- * Followed by scanline data for AND mask, then XOR mask.
- * Each scanline is padded to a 32-bit boundary.
- */
-}
-#include "vmware_pack_end.h"
-SVGAGBColorCursorHeader;
-
-
-/*
- * Provide a new large cursor image, in 32-bit BGRA format.
- *
- * Should only be used for CursorMob functionality
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 hotspotX;
- uint32 hotspotY;
- uint32 width;
- uint32 height;
- /* Followed by scanline data */
-}
-#include "vmware_pack_end.h"
-SVGAGBAlphaCursorHeader;
-
- /*
- * Define the SVGA guest backed cursor types
- */
+#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
+#define SVGA_CMD_MAX_ARGS 64
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 x;
+ uint32 y;
+ uint32 width;
+ uint32 height;
+} SVGAFifoCmdUpdate;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 srcX;
+ uint32 srcY;
+ uint32 destX;
+ uint32 destY;
+ uint32 width;
+ uint32 height;
+} SVGAFifoCmdRectCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 srcX;
+ uint32 srcY;
+ uint32 destX;
+ uint32 destY;
+ uint32 width;
+ uint32 height;
+ uint32 rop;
+} SVGAFifoCmdRectRopCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 id;
+ uint32 hotspotX;
+ uint32 hotspotY;
+ uint32 width;
+ uint32 height;
+ uint32 andMaskDepth;
+ uint32 xorMaskDepth;
+
+} SVGAFifoCmdDefineCursor;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 id;
+ uint32 hotspotX;
+ uint32 hotspotY;
+ uint32 width;
+ uint32 height;
+
+} SVGAFifoCmdDefineAlphaCursor;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 hotspotX;
+ uint32 hotspotY;
+ uint32 width;
+ uint32 height;
+ uint32 andMaskDepth;
+ uint32 xorMaskDepth;
+
+} SVGAGBColorCursorHeader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 hotspotX;
+ uint32 hotspotY;
+ uint32 width;
+ uint32 height;
+
+} SVGAGBAlphaCursorHeader;
+#pragma pack(pop)
typedef enum {
- SVGA_COLOR_CURSOR = 0,
- SVGA_ALPHA_CURSOR = 1,
+ SVGA_COLOR_CURSOR = 0,
+ SVGA_ALPHA_CURSOR = 1,
} SVGAGBCursorType;
-/*
- * Provide a new large cursor image.
- *
- * Should only be used for CursorMob functionality
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAGBCursorType type;
- union {
- SVGAGBColorCursorHeader colorHeader;
- SVGAGBAlphaCursorHeader alphaHeader;
- } header;
- uint32 sizeInBytes;
- /*
- * Followed by the cursor data
- */
-}
-#include "vmware_pack_end.h"
-SVGAGBCursorHeader;
-
-
-/*
- * SVGA_CMD_UPDATE_VERBOSE --
- *
- * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
- * 'reason' value, an opaque cookie which is used by internal
- * debugging tools. Third party drivers should not use this
- * command.
- *
- * Availability:
- * SVGA_CAP_EXTENDED_FIFO
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 x;
- uint32 y;
- uint32 width;
- uint32 height;
- uint32 reason;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdUpdateVerbose;
-
-
-/*
- * SVGA_CMD_FRONT_ROP_FILL --
- *
- * This is a hint which tells the SVGA device that the driver has
- * just filled a rectangular region of the GFB with a solid
- * color. Instead of reading these pixels from the GFB, the device
- * can assume that they all equal 'color'. This is primarily used
- * for remote desktop protocols.
- *
- * Availability:
- * SVGA_FIFO_CAP_ACCELFRONT
- */
-
-#define SVGA_ROP_COPY 0x03
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 color; /* In the same format as the GFB */
- uint32 x;
- uint32 y;
- uint32 width;
- uint32 height;
- uint32 rop; /* Must be SVGA_ROP_COPY */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdFrontRopFill;
-
-
-/*
- * SVGA_CMD_FENCE --
- *
- * Insert a synchronization fence. When the SVGA device reaches
- * this command, it will copy the 'fence' value into the
- * SVGA_FIFO_FENCE register. It will also compare the fence against
- * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
- * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
- * raise this interrupt.
- *
- * Availability:
- * SVGA_FIFO_FENCE for this command,
- * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 fence;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdFence;
-
-
-/*
- * SVGA_CMD_ESCAPE --
- *
- * Send an extended or vendor-specific variable length command.
- * This is used for video overlay, third party plugins, and
- * internal debugging tools. See svga_escape.h
- *
- * Availability:
- * SVGA_FIFO_CAP_ESCAPE
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 nsid;
- uint32 size;
- /* followed by 'size' bytes of data */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdEscape;
-
-
-/*
- * SVGA_CMD_DEFINE_SCREEN --
- *
- * Define or redefine an SVGAScreenObject. See the description of
- * SVGAScreenObject above. The video driver is responsible for
- * generating new screen IDs. They should be small positive
- * integers. The virtual device will have an implementation
- * specific upper limit on the number of screen IDs
- * supported. Drivers are responsible for recycling IDs. The first
- * valid ID is zero.
- *
- * - Interaction with other registers:
- *
- * For backwards compatibility, when the GFB mode registers (WIDTH,
- * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
- * deletes all screens other than screen #0, and redefines screen
- * #0 according to the specified mode. Drivers that use
- * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
- *
- * If you use screen objects, do not use the legacy multi-mon
- * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAScreenObject screen; /* Variable-length according to version */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDefineScreen;
-
-
-/*
- * SVGA_CMD_DESTROY_SCREEN --
- *
- * Destroy an SVGAScreenObject. Its ID is immediately available for
- * re-use.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 screenId;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDestroyScreen;
-
-
-/*
- * SVGA_CMD_DEFINE_GMRFB --
- *
- * This command sets a piece of SVGA device state called the
- * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
- * piece of light-weight state which identifies the location and
- * format of an image in guest memory or in BAR1. The GMRFB has
- * an arbitrary size, and it doesn't need to match the geometry
- * of the GFB or any screen object.
- *
- * The GMRFB can be redefined as often as you like. You could
- * always use the same GMRFB, you could redefine it before
- * rendering from a different guest screen, or you could even
- * redefine it before every blit.
- *
- * There are multiple ways to use this command. The simplest way is
- * to use it to move the framebuffer either to elsewhere in the GFB
- * (BAR1) memory region, or to a user-defined GMR. This lets a
- * driver use a framebuffer allocated entirely out of normal system
- * memory, which we encourage.
- *
- * Another way to use this command is to set up a ring buffer of
- * updates in GFB memory. If a driver wants to ensure that no
- * frames are skipped by the SVGA device, it is important that the
- * driver not modify the source data for a blit until the device is
- * done processing the command. One efficient way to accomplish
- * this is to use a ring of small DMA buffers. Each buffer is used
- * for one blit, then we move on to the next buffer in the
- * ring. The FENCE mechanism is used to protect each buffer from
- * re-use until the device is finished with that buffer's
- * corresponding blit.
- *
- * This command does not affect the meaning of SVGA_CMD_UPDATE.
- * UPDATEs always occur from the legacy GFB memory area. This
- * command has no support for pseudocolor GMRFBs. Currently only
- * true-color 15, 16, and 24-bit depths are supported. Future
- * devices may expose capabilities for additional framebuffer
- * formats.
- *
- * The default GMRFB value is undefined. Drivers must always send
- * this command at least once before performing any blit from the
- * GMRFB.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAGuestPtr ptr;
- uint32 bytesPerLine;
- SVGAGMRImageFormat format;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDefineGMRFB;
-
-
-/*
- * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
- *
- * This is a guest-to-host blit. It performs a DMA operation to
- * copy a rectangular region of pixels from the current GMRFB to
- * a ScreenObject.
- *
- * The destination coordinate may be specified relative to a
- * screen's origin. The provided screen ID must be valid.
- *
- * The SVGA device is guaranteed to finish reading from the GMRFB
- * by the time any subsequent FENCE commands are reached.
- *
- * This command consumes an annotation. See the
- * SVGA_CMD_ANNOTATION_* commands for details.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGASignedPoint srcOrigin;
- SVGASignedRect destRect;
- uint32 destScreenId;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdBlitGMRFBToScreen;
-
-
-/*
- * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
- *
- * This is a host-to-guest blit. It performs a DMA operation to
- * copy a rectangular region of pixels from a single ScreenObject
- * back to the current GMRFB.
- *
- * The source coordinate is specified relative to a screen's
- * origin. The provided screen ID must be valid. If any parameters
- * are invalid, the resulting pixel values are undefined.
- *
- * The SVGA device is guaranteed to finish writing to the GMRFB by
- * the time any subsequent FENCE commands are reached.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGASignedPoint destOrigin;
- SVGASignedRect srcRect;
- uint32 srcScreenId;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdBlitScreenToGMRFB;
-
-
-/*
- * SVGA_CMD_ANNOTATION_FILL --
- *
- * The annotation commands have been deprecated, should not be used
- * by new drivers. They used to provide performance hints to the SVGA
- * device about the content of screen updates, but newer SVGA devices
- * ignore these.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGAColorBGRX color;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdAnnotationFill;
-
-
-/*
- * SVGA_CMD_ANNOTATION_COPY --
- *
- * The annotation commands have been deprecated, should not be used
- * by new drivers. They used to provide performance hints to the SVGA
- * device about the content of screen updates, but newer SVGA devices
- * ignore these.
- *
- * Availability:
- * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- SVGASignedPoint srcOrigin;
- uint32 srcScreenId;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdAnnotationCopy;
-
-
-/*
- * SVGA_CMD_DEFINE_GMR2 --
- *
- * Define guest memory region v2. See the description of GMRs above.
- *
- * Availability:
- * SVGA_CAP_GMR2
- */
-
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 gmrId;
- uint32 numPages;
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdDefineGMR2;
-
-
-/*
- * SVGA_CMD_REMAP_GMR2 --
- *
- * Remap guest memory region v2. See the description of GMRs above.
- *
- * This command allows guest to modify a portion of an existing GMR by
- * invalidating it or reassigning it to different guest physical pages.
- * The pages are identified by physical page number (PPN). The pages
- * are assumed to be pinned and valid for DMA operations.
- *
- * Description of command flags:
- *
- * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
- * The PPN list must not overlap with the remap region (this can be
- * handled trivially by referencing a separate GMR). If flag is
- * disabled, PPN list is appended to SVGARemapGMR command.
- *
- * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
- * it is in PPN32 format.
- *
- * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
- * A single PPN can be used to invalidate a portion of a GMR or
- * map it to to a single guest scratch page.
- *
- * Availability:
- * SVGA_CAP_GMR2
- */
+#pragma pack(push, 1)
+typedef struct {
+ SVGAGBCursorType type;
+ union {
+ SVGAGBColorCursorHeader colorHeader;
+ SVGAGBAlphaCursorHeader alphaHeader;
+ } header;
+ uint32 sizeInBytes;
+
+} SVGAGBCursorHeader;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 x;
+ uint32 y;
+ uint32 width;
+ uint32 height;
+ uint32 reason;
+} SVGAFifoCmdUpdateVerbose;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 color;
+ uint32 x;
+ uint32 y;
+ uint32 width;
+ uint32 height;
+ uint32 rop;
+} SVGAFifoCmdFrontRopFill;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 fence;
+} SVGAFifoCmdFence;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 nsid;
+ uint32 size;
+
+} SVGAFifoCmdEscape;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAScreenObject screen;
+} SVGAFifoCmdDefineScreen;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 screenId;
+} SVGAFifoCmdDestroyScreen;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAGuestPtr ptr;
+ uint32 bytesPerLine;
+ SVGAGMRImageFormat format;
+} SVGAFifoCmdDefineGMRFB;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGASignedPoint srcOrigin;
+ SVGASignedRect destRect;
+ uint32 destScreenId;
+} SVGAFifoCmdBlitGMRFBToScreen;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGASignedPoint destOrigin;
+ SVGASignedRect srcRect;
+ uint32 srcScreenId;
+} SVGAFifoCmdBlitScreenToGMRFB;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGAColorBGRX color;
+} SVGAFifoCmdAnnotationFill;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ SVGASignedPoint srcOrigin;
+ uint32 srcScreenId;
+} SVGAFifoCmdAnnotationCopy;
+#pragma pack(pop)
+
+#pragma pack(push, 1)
+typedef struct {
+ uint32 gmrId;
+ uint32 numPages;
+} SVGAFifoCmdDefineGMR2;
+#pragma pack(pop)
typedef enum {
- SVGA_REMAP_GMR2_PPN32 = 0,
- SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
- SVGA_REMAP_GMR2_PPN64 = (1 << 1),
- SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
+ SVGA_REMAP_GMR2_PPN32 = 0,
+ SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
+ SVGA_REMAP_GMR2_PPN64 = (1 << 1),
+ SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
} SVGARemapGMR2Flags;
-typedef
-#include "vmware_pack_begin.h"
-struct {
- uint32 gmrId;
- SVGARemapGMR2Flags flags;
- uint32 offsetPages; /* offset in pages to begin remap */
- uint32 numPages; /* number of pages to remap */
- /*
- * Followed by additional data depending on SVGARemapGMR2Flags.
- *
- * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
- * Otherwise an array of page descriptors in PPN32 or PPN64 format
- * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
- * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
- */
-}
-#include "vmware_pack_end.h"
-SVGAFifoCmdRemapGMR2;
-
-
-/*
- * Size of SVGA device memory such as frame buffer and FIFO.
- */
-#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */
-#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
-#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
-#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
-#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
-#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
+#pragma pack(push, 1)
+typedef struct {
+ uint32 gmrId;
+ SVGARemapGMR2Flags flags;
+ uint32 offsetPages;
+ uint32 numPages;
+
+} SVGAFifoCmdRemapGMR2;
+#pragma pack(pop)
+
+#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480)
+#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
+#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
+#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
+#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
+#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024)
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
-#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
+#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024)
#if defined(VMX86_SERVER)
-#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
-#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
-#define SVGA_FIFO_SIZE (256 * 1024)
-#define SVGA_FIFO_SIZE_3D (516 * 1024)
-#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
-#define SVGA_AUTODETECT_DEFAULT FALSE
+#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
+#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
+#define SVGA_FIFO_SIZE (256 * 1024)
+#define SVGA_FIFO_SIZE_3D (516 * 1024)
+#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
+#define SVGA_AUTODETECT_DEFAULT FALSE
#else
-#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
-#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
-#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
-#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
-#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
-#define SVGA_AUTODETECT_DEFAULT TRUE
+#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
+#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
+#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
+#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
+#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
+#define SVGA_AUTODETECT_DEFAULT TRUE
#endif
-#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
-#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
-
-#define SVGA_PCI_REGS_PAGES (1)
+#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
+#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
#endif
diff --git a/drivers/gpu/drm/vmwgfx/device_include/svga_types.h b/drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
similarity index 95%
rename from drivers/gpu/drm/vmwgfx/device_include/svga_types.h
rename to drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
index f5f79b114fac5ebbf36e8488a30c9d455b3bbd3c..35bd2852189f95e654c92eeffff25663908797b9 100644
--- a/drivers/gpu/drm/vmwgfx/device_include/svga_types.h
+++ b/drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/**********************************************************
- * Copyright 2015 VMware, Inc.
+ * Copyright 2015-2021 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
@@ -23,8 +23,9 @@
* SOFTWARE.
*
**********************************************************/
-#ifndef _SVGA_TYPES_H_
-#define _SVGA_TYPES_H_
+#ifndef VM_BASIC_TYPES_H
+#define VM_BASIC_TYPES_H
+
#include <linux/kernel.h>
#include <linux/mm.h>
#include <asm/page.h>
@@ -50,6 +51,13 @@ typedef bool Bool;
#define CONST64U(x) x##ULL
+#ifndef MBYTES_SHIFT
+#define MBYTES_SHIFT 20
+#endif
+#ifndef MBYTES_2_BYTES
+#define MBYTES_2_BYTES(_nbytes) ((uint64)(_nbytes) << MBYTES_SHIFT)
+#endif
+
/*
* MKS Guest Stats types
*/
diff --git a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
deleted file mode 100644
index 75308bd0d97051da1b13e343d5eaed365dc273f5..0000000000000000000000000000000000000000
--- a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/compiler.h>
diff --git a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h b/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
deleted file mode 100644
index e93d6f28b68ceda969a00dd0a60de2ed379c5810..0000000000000000000000000000000000000000
--- a/drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
+++ /dev/null
@@ -1,2 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-__packed
diff --git a/drivers/gpu/drm/vmwgfx/vmw_surface_cache.h b/drivers/gpu/drm/vmwgfx/vmw_surface_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b0d87c5f58d8ed711d2c90965e74bbb9ad3101f1
--- /dev/null
+++ b/drivers/gpu/drm/vmwgfx/vmw_surface_cache.h
@@ -0,0 +1,539 @@
+/**********************************************************
+ * Copyright 2021 VMware, Inc.
+ * SPDX-License-Identifier: GPL-2.0 OR MIT
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ **********************************************************/
+
+#ifndef VMW_SURFACE_CACHE_H
+#define VMW_SURFACE_CACHE_H
+
+#include "device_include/svga3d_surfacedefs.h"
+
+#include <drm/vmwgfx_drm.h>
+
+static inline u32 clamped_umul32(u32 a, u32 b)
+{
+ uint64_t tmp = (uint64_t) a*b;
+ return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
+}
+
+/**
+ * vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
+ * given format.
+ */
+static inline const SVGA3dSurfaceDesc *
+vmw_surface_get_desc(SVGA3dSurfaceFormat format)
+{
+ if (format < ARRAY_SIZE(g_SVGA3dSurfaceDescs))
+ return &g_SVGA3dSurfaceDescs[format];
+
+ return &g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_INVALID];
+}
+
+/**
+ * vmw_surface_get_mip_size - Given a base level size and the mip level,
+ * compute the size of the mip level.
+ */
+static inline struct drm_vmw_size
+vmw_surface_get_mip_size(struct drm_vmw_size base_level, u32 mip_level)
+{
+ struct drm_vmw_size size = {
+ .width = max_t(u32, base_level.width >> mip_level, 1),
+ .height = max_t(u32, base_level.height >> mip_level, 1),
+ .depth = max_t(u32, base_level.depth >> mip_level, 1)
+ };
+
+ return size;
+}
+
+static inline void
+vmw_surface_get_size_in_blocks(const SVGA3dSurfaceDesc *desc,
+ const struct drm_vmw_size *pixel_size,
+ SVGA3dSize *block_size)
+{
+ block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
+ desc->blockSize.width);
+ block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
+ desc->blockSize.height);
+ block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
+ desc->blockSize.depth);
+}
+
+static inline bool
+vmw_surface_is_planar_surface(const SVGA3dSurfaceDesc *desc)
+{
+ return (desc->blockDesc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
+}
+
+static inline u32
+vmw_surface_calculate_pitch(const SVGA3dSurfaceDesc *desc,
+ const struct drm_vmw_size *size)
+{
+ u32 pitch;
+ SVGA3dSize blocks;
+
+ vmw_surface_get_size_in_blocks(desc, size, &blocks);
+
+ pitch = blocks.width * desc->pitchBytesPerBlock;
+
+ return pitch;
+}
+
+/**
+ * vmw_surface_get_image_buffer_size - Calculates image buffer size.
+ *
+ * Return the number of bytes of buffer space required to store one image of a
+ * surface, optionally using the specified pitch.
+ *
+ * If pitch is zero, it is assumed that rows are tightly packed.
+ *
+ * This function is overflow-safe. If the result would have overflowed, instead
+ * we return MAX_UINT32.
+ */
+static inline u32
+vmw_surface_get_image_buffer_size(const SVGA3dSurfaceDesc *desc,
+ const struct drm_vmw_size *size,
+ u32 pitch)
+{
+ SVGA3dSize image_blocks;
+ u32 slice_size, total_size;
+
+ vmw_surface_get_size_in_blocks(desc, size, &image_blocks);
+
+ if (vmw_surface_is_planar_surface(desc)) {
+ total_size = clamped_umul32(image_blocks.width,
+ image_blocks.height);
+ total_size = clamped_umul32(total_size, image_blocks.depth);
+ total_size = clamped_umul32(total_size, desc->bytesPerBlock);
+ return total_size;
+ }
+
+ if (pitch == 0)
+ pitch = vmw_surface_calculate_pitch(desc, size);
+
+ slice_size = clamped_umul32(image_blocks.height, pitch);
+ total_size = clamped_umul32(slice_size, image_blocks.depth);
+
+ return total_size;
+}
+
+/**
+ * vmw_surface_get_serialized_size - Get the serialized size for the image.
+ */
+static inline u32
+vmw_surface_get_serialized_size(SVGA3dSurfaceFormat format,
+ struct drm_vmw_size base_level_size,
+ u32 num_mip_levels,
+ u32 num_layers)
+{
+ const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
+ u32 total_size = 0;
+ u32 mip;
+
+ for (mip = 0; mip < num_mip_levels; mip++) {
+ struct drm_vmw_size size =
+ vmw_surface_get_mip_size(base_level_size, mip);
+ total_size += vmw_surface_get_image_buffer_size(desc,
+ &size, 0);
+ }
+
+ return total_size * num_layers;
+}
+
+/**
+ * vmw_surface_get_serialized_size_extended - Returns the number of bytes
+ * required for a surface with given parameters. Support for sample count.
+ */
+static inline u32
+vmw_surface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
+ struct drm_vmw_size base_level_size,
+ u32 num_mip_levels,
+ u32 num_layers,
+ u32 num_samples)
+{
+ uint64_t total_size =
+ vmw_surface_get_serialized_size(format,
+ base_level_size,
+ num_mip_levels,
+ num_layers);
+ total_size *= max_t(u32, 1, num_samples);
+
+ return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
+}
+
+/**
+ * vmw_surface_get_pixel_offset - Compute the offset (in bytes) to a pixel
+ * in an image (or volume).
+ *
+ * @width: The image width in pixels.
+ * @height: The image height in pixels
+ */
+static inline u32
+vmw_surface_get_pixel_offset(SVGA3dSurfaceFormat format,
+ u32 width, u32 height,
+ u32 x, u32 y, u32 z)
+{
+ const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
+ const u32 bw = desc->blockSize.width, bh = desc->blockSize.height;
+ const u32 bd = desc->blockSize.depth;
+ const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
+ desc->bytesPerBlock;
+ const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
+ const u32 offset = (z / bd * imgstride +
+ y / bh * rowstride +
+ x / bw * desc->bytesPerBlock);
+ return offset;
+}
+
+static inline u32
+vmw_surface_get_image_offset(SVGA3dSurfaceFormat format,
+ struct drm_vmw_size baseLevelSize,
+ u32 numMipLevels,
+ u32 face,
+ u32 mip)
+
+{
+ u32 offset;
+ u32 mipChainBytes;
+ u32 mipChainBytesToLevel;
+ u32 i;
+ const SVGA3dSurfaceDesc *desc;
+ struct drm_vmw_size mipSize;
+ u32 bytes;
+
+ desc = vmw_surface_get_desc(format);
+
+ mipChainBytes = 0;
+ mipChainBytesToLevel = 0;
+ for (i = 0; i < numMipLevels; i++) {
+ mipSize = vmw_surface_get_mip_size(baseLevelSize, i);
+ bytes = vmw_surface_get_image_buffer_size(desc, &mipSize, 0);
+ mipChainBytes += bytes;
+ if (i < mip)
+ mipChainBytesToLevel += bytes;
+ }
+
+ offset = mipChainBytes * face + mipChainBytesToLevel;
+
+ return offset;
+}
+
+
+/**
+ * vmw_surface_is_gb_screen_target_format - Is the specified format usable as
+ * a ScreenTarget?
+ * (with just the GBObjects cap-bit
+ * set)
+ * @format: format to queried
+ *
+ * RETURNS:
+ * true if queried format is valid for screen targets
+ */
+static inline bool
+vmw_surface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
+{
+ return (format == SVGA3D_X8R8G8B8 ||
+ format == SVGA3D_A8R8G8B8 ||
+ format == SVGA3D_R5G6B5 ||
+ format == SVGA3D_X1R5G5B5 ||
+ format == SVGA3D_A1R5G5B5 ||
+ format == SVGA3D_P8);
+}
+
+
+/**
+ * vmw_surface_is_dx_screen_target_format - Is the specified format usable as
+ * a ScreenTarget?
+ * (with DX10 enabled)
+ *
+ * @format: format to queried
+ *
+ * Results:
+ * true if queried format is valid for screen targets
+ */
+static inline bool
+vmw_surface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
+{
+ return (format == SVGA3D_R8G8B8A8_UNORM ||
+ format == SVGA3D_B8G8R8A8_UNORM ||
+ format == SVGA3D_B8G8R8X8_UNORM);
+}
+
+
+/**
+ * vmw_surface_is_screen_target_format - Is the specified format usable as a
+ * ScreenTarget?
+ * (for some combination of caps)
+ *
+ * @format: format to queried
+ *
+ * Results:
+ * true if queried format is valid for screen targets
+ */
+static inline bool
+vmw_surface_is_screen_target_format(SVGA3dSurfaceFormat format)
+{
+ if (vmw_surface_is_gb_screen_target_format(format)) {
+ return true;
+ }
+ return vmw_surface_is_dx_screen_target_format(format);
+}
+
+/**
+ * struct vmw_surface_mip - Mimpmap level information
+ * @bytes: Bytes required in the backing store of this mipmap level.
+ * @img_stride: Byte stride per image.
+ * @row_stride: Byte stride per block row.
+ * @size: The size of the mipmap.
+ */
+struct vmw_surface_mip {
+ size_t bytes;
+ size_t img_stride;
+ size_t row_stride;
+ struct drm_vmw_size size;
+
+};
+
+/**
+ * struct vmw_surface_cache - Cached surface information
+ * @desc: Pointer to the surface descriptor
+ * @mip: Array of mipmap level information. Valid size is @num_mip_levels.
+ * @mip_chain_bytes: Bytes required in the backing store for the whole chain
+ * of mip levels.
+ * @sheet_bytes: Bytes required in the backing store for a sheet
+ * representing a single sample.
+ * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
+ * a chain.
+ * @num_layers: Number of slices in an array texture or number of faces in
+ * a cubemap texture.
+ */
+struct vmw_surface_cache {
+ const SVGA3dSurfaceDesc *desc;
+ struct vmw_surface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
+ size_t mip_chain_bytes;
+ size_t sheet_bytes;
+ u32 num_mip_levels;
+ u32 num_layers;
+};
+
+/**
+ * struct vmw_surface_loc - Surface location
+ * @sheet: The multisample sheet.
+ * @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
+ * mip_level.
+ * @x: X coordinate.
+ * @y: Y coordinate.
+ * @z: Z coordinate.
+ */
+struct vmw_surface_loc {
+ u32 sheet;
+ u32 sub_resource;
+ u32 x, y, z;
+};
+
+/**
+ * vmw_surface_subres - Compute the subresource from layer and mipmap.
+ * @cache: Surface layout data.
+ * @mip_level: The mipmap level.
+ * @layer: The surface layer (face or array slice).
+ *
+ * Return: The subresource.
+ */
+static inline u32 vmw_surface_subres(const struct vmw_surface_cache *cache,
+ u32 mip_level, u32 layer)
+{
+ return cache->num_mip_levels * layer + mip_level;
+}
+
+/**
+ * vmw_surface_setup_cache - Build a surface cache entry
+ * @size: The surface base level dimensions.
+ * @format: The surface format.
+ * @num_mip_levels: Number of mipmap levels.
+ * @num_layers: Number of layers.
+ * @cache: Pointer to a struct vmw_surface_cach object to be filled in.
+ *
+ * Return: Zero on success, -EINVAL on invalid surface layout.
+ */
+static inline int vmw_surface_setup_cache(const struct drm_vmw_size *size,
+ SVGA3dSurfaceFormat format,
+ u32 num_mip_levels,
+ u32 num_layers,
+ u32 num_samples,
+ struct vmw_surface_cache *cache)
+{
+ const SVGA3dSurfaceDesc *desc;
+ u32 i;
+
+ memset(cache, 0, sizeof(*cache));
+ cache->desc = desc = vmw_surface_get_desc(format);
+ cache->num_mip_levels = num_mip_levels;
+ cache->num_layers = num_layers;
+ for (i = 0; i < cache->num_mip_levels; i++) {
+ struct vmw_surface_mip *mip = &cache->mip[i];
+
+ mip->size = vmw_surface_get_mip_size(*size, i);
+ mip->bytes = vmw_surface_get_image_buffer_size
+ (desc, &mip->size, 0);
+ mip->row_stride =
+ __KERNEL_DIV_ROUND_UP(mip->size.width,
+ desc->blockSize.width) *
+ desc->bytesPerBlock * num_samples;
+ if (!mip->row_stride)
+ goto invalid_dim;
+
+ mip->img_stride =
+ __KERNEL_DIV_ROUND_UP(mip->size.height,
+ desc->blockSize.height) *
+ mip->row_stride;
+ if (!mip->img_stride)
+ goto invalid_dim;
+
+ cache->mip_chain_bytes += mip->bytes;
+ }
+ cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
+ if (!cache->sheet_bytes)
+ goto invalid_dim;
+
+ return 0;
+
+invalid_dim:
+ VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
+ return -EINVAL;
+}
+
+/**
+ * vmw_surface_get_loc - Get a surface location from an offset into the
+ * backing store
+ * @cache: Surface layout data.
+ * @loc: Pointer to a struct vmw_surface_loc to be filled in.
+ * @offset: Offset into the surface backing store.
+ */
+static inline void
+vmw_surface_get_loc(const struct vmw_surface_cache *cache,
+ struct vmw_surface_loc *loc,
+ size_t offset)
+{
+ const struct vmw_surface_mip *mip = &cache->mip[0];
+ const SVGA3dSurfaceDesc *desc = cache->desc;
+ u32 layer;
+ int i;
+
+ loc->sheet = offset / cache->sheet_bytes;
+ offset -= loc->sheet * cache->sheet_bytes;
+
+ layer = offset / cache->mip_chain_bytes;
+ offset -= layer * cache->mip_chain_bytes;
+ for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
+ if (mip->bytes > offset)
+ break;
+ offset -= mip->bytes;
+ }
+
+ loc->sub_resource = vmw_surface_subres(cache, i, layer);
+ loc->z = offset / mip->img_stride;
+ offset -= loc->z * mip->img_stride;
+ loc->z *= desc->blockSize.depth;
+ loc->y = offset / mip->row_stride;
+ offset -= loc->y * mip->row_stride;
+ loc->y *= desc->blockSize.height;
+ loc->x = offset / desc->bytesPerBlock;
+ loc->x *= desc->blockSize.width;
+}
+
+/**
+ * vmw_surface_inc_loc - Clamp increment a surface location with one block
+ * size
+ * in each dimension.
+ * @loc: Pointer to a struct vmw_surface_loc to be incremented.
+ *
+ * When computing the size of a range as size = end - start, the range does not
+ * include the end element. However a location representing the last byte
+ * of a touched region in the backing store *is* included in the range.
+ * This function modifies such a location to match the end definition
+ * given as start + size which is the one used in a SVGA3dBox.
+ */
+static inline void
+vmw_surface_inc_loc(const struct vmw_surface_cache *cache,
+ struct vmw_surface_loc *loc)
+{
+ const SVGA3dSurfaceDesc *desc = cache->desc;
+ u32 mip = loc->sub_resource % cache->num_mip_levels;
+ const struct drm_vmw_size *size = &cache->mip[mip].size;
+
+ loc->sub_resource++;
+ loc->x += desc->blockSize.width;
+ if (loc->x > size->width)
+ loc->x = size->width;
+ loc->y += desc->blockSize.height;
+ if (loc->y > size->height)
+ loc->y = size->height;
+ loc->z += desc->blockSize.depth;
+ if (loc->z > size->depth)
+ loc->z = size->depth;
+}
+
+/**
+ * vmw_surface_min_loc - The start location in a subresource
+ * @cache: Surface layout data.
+ * @sub_resource: The subresource.
+ * @loc: Pointer to a struct vmw_surface_loc to be filled in.
+ */
+static inline void
+vmw_surface_min_loc(const struct vmw_surface_cache *cache,
+ u32 sub_resource,
+ struct vmw_surface_loc *loc)
+{
+ loc->sheet = 0;
+ loc->sub_resource = sub_resource;
+ loc->x = loc->y = loc->z = 0;
+}
+
+/**
+ * vmw_surface_min_loc - The end location in a subresource
+ * @cache: Surface layout data.
+ * @sub_resource: The subresource.
+ * @loc: Pointer to a struct vmw_surface_loc to be filled in.
+ *
+ * Following the end definition given in vmw_surface_inc_loc(),
+ * Compute the end location of a surface subresource.
+ */
+static inline void
+vmw_surface_max_loc(const struct vmw_surface_cache *cache,
+ u32 sub_resource,
+ struct vmw_surface_loc *loc)
+{
+ const struct drm_vmw_size *size;
+ u32 mip;
+
+ loc->sheet = 0;
+ loc->sub_resource = sub_resource + 1;
+ mip = sub_resource % cache->num_mip_levels;
+ size = &cache->mip[mip].size;
+ loc->x = size->width;
+ loc->y = size->height;
+ loc->z = size->depth;
+}
+
+
+#endif /* VMW_SURFACE_CACHE_H */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c b/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
index ea6d8c86985f6687c3b5282a43fccfc79f2e30e0..6f27d69bad0ed48613499ff2cd0efed1a323e782 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
@@ -844,7 +844,7 @@ static int vmw_emit_set_rt(struct vmw_ctx_binding_state *cbs)
size_t cmd_size, view_id_size;
const struct vmw_resource *ctx = vmw_cbs_context(cbs);
- vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
+ vmw_collect_view_ids(cbs, loc, SVGA3D_DX_MAX_RENDER_TARGETS);
view_id_size = cbs->bind_cmd_count*sizeof(uint32);
cmd_size = sizeof(*cmd) + view_id_size;
cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
@@ -1440,7 +1440,7 @@ u32 vmw_binding_dirtying(enum vmw_ctx_binding_type binding_type)
static void vmw_binding_build_asserts(void)
{
BUILD_BUG_ON(SVGA3D_NUM_SHADERTYPE_DX10 != 3);
- BUILD_BUG_ON(SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS > SVGA3D_RT_MAX);
+ BUILD_BUG_ON(SVGA3D_DX_MAX_RENDER_TARGETS > SVGA3D_RT_MAX);
BUILD_BUG_ON(sizeof(uint32) != sizeof(u32));
/*
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
index dffe3804ad3e5499d27745dfc263929d64ea9330..4446758b688006f5ba1215e006a00d7b2fad30d3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_context.c
@@ -185,7 +185,7 @@ static int vmw_gb_context_init(struct vmw_private *dev_priv,
container_of(res, struct vmw_user_context, res);
res->backup_size = (dx ? sizeof(SVGADXContextMobFormat) :
- SVGA3D_CONTEXT_DATA_SIZE);
+ sizeof(SVGAGBContextData));
ret = vmw_resource_init(dev_priv, res, true,
res_free,
dx ? &vmw_dx_context_func :
@@ -259,7 +259,7 @@ static int vmw_context_init(struct vmw_private *dev_priv,
goto out_early;
}
- if (unlikely(res->id >= SVGA3D_MAX_CONTEXT_IDS)) {
+ if (unlikely(res->id >= SVGA3D_HB_MAX_CONTEXT_IDS)) {
DRM_ERROR("Out of hw context ids.\n");
vmw_resource_unreference(&res);
return -ENOMEM;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c b/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
index 04fc67d535636e12a583ca7325f8fe4a87a9f8d8..829df395c2ed7f7b44b5f1df2f08aeeb0f7880a3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
@@ -31,8 +31,8 @@
struct svga_3d_compat_cap {
- SVGA3dCapsRecordHeader header;
- SVGA3dCapPair pairs[SVGA3D_DEVCAP_MAX];
+ SVGA3dFifoCapsRecordHeader header;
+ SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
};
@@ -64,14 +64,14 @@ static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce,
if (size < pair_offset)
return -EINVAL;
- max_size = (size - pair_offset) / sizeof(SVGA3dCapPair);
+ max_size = (size - pair_offset) / sizeof(SVGA3dFifoCapPair);
if (max_size > SVGA3D_DEVCAP_MAX)
max_size = SVGA3D_DEVCAP_MAX;
compat_cap->header.length =
- (pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);
- compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
+ (pair_offset + max_size * sizeof(SVGA3dFifoCapPair)) / sizeof(u32);
+ compat_cap->header.type = SVGA3D_FIFO_CAPS_RECORD_DEVCAPS;
for (i = 0; i < max_size; ++i) {
compat_cap->pairs[i][0] = i;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h b/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
index b7c43e5f07c336e10f1ff7b6d4e60d39fe843cb2..f70e923ac3e6f7118e27675a91542a51f203783d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
@@ -30,7 +30,7 @@
#include "vmwgfx_drv.h"
-#include "device_include/svga3d_caps.h"
+#include "device_include/svga_reg.h"
int vmw_devcaps_create(struct vmw_private *vmw);
void vmw_devcaps_destroy(struct vmw_private *vmw);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 48a62fb0da2f30ada0837a72b050685ecec691fb..086dc75e7b42bd2730c67a5a6dfdf7e29117c4d9 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -891,9 +891,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
mem_size *= 3;
dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
- dev_priv->prim_bb_mem =
- vmw_read(dev_priv,
- SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
+ dev_priv->max_primary_mem =
+ vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
dev_priv->max_mob_size =
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
dev_priv->stdu_max_width =
@@ -912,7 +911,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
} else {
dev_priv->texture_max_width = 8192;
dev_priv->texture_max_height = 8192;
- dev_priv->prim_bb_mem = dev_priv->vram_size;
+ dev_priv->max_primary_mem = dev_priv->vram_size;
}
vmw_print_capabilities(dev_priv->capabilities);
@@ -936,7 +935,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
(unsigned)dev_priv->memory_size / 1024);
}
DRM_INFO("Maximum display memory size is %llu kiB\n",
- (uint64_t)dev_priv->prim_bb_mem / 1024);
+ (uint64_t)dev_priv->max_primary_mem / 1024);
/* Need mmio memory to check for fifo pitchlock cap. */
if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 9422967659d7d17bc4a41cecec11deef5bba330c..0dd5a3e06f5fa5d5125aca52de14bc8707f14c15 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -491,7 +491,7 @@ struct vmw_private {
resource_size_t io_start;
resource_size_t vram_start;
resource_size_t vram_size;
- resource_size_t prim_bb_mem;
+ resource_size_t max_primary_mem;
void __iomem *rmmio;
u32 *fifo_mem;
resource_size_t fifo_mem_size;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index cc8b1d943c55d1c1362855a4f8dc5a266ec4d114..5f2ffa9de5c8f63c12f2cd7b20e6f57c8f9512c0 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -2365,7 +2365,7 @@ static int vmw_cmd_dx_set_rendertargets(struct vmw_private *dev_priv,
sizeof(SVGA3dRenderTargetViewId);
int ret;
- if (num_rt_view > SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS) {
+ if (num_rt_view > SVGA3D_DX_MAX_RENDER_TARGETS) {
VMW_DEBUG_USER("Invalid DX Rendertarget binding.\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index c34f61ac4ce40230ebd20aa478cdf002bcd5c8c3..28af34ab6ed611d8ec702bc7a690e2cbbd0f9071 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -58,7 +58,7 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
param->value = vmw_fifo_caps(dev_priv);
break;
case DRM_VMW_PARAM_MAX_FB_SIZE:
- param->value = dev_priv->prim_bb_mem;
+ param->value = dev_priv->max_primary_mem;
break;
case DRM_VMW_PARAM_FIFO_HW_VERSION:
{
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 220f9fd0d42025a25bf2a831b8f874632e4b1489..2ddf4932d62c03ce5d808e5539dec83da24a1a57 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1487,7 +1487,7 @@ static int vmw_kms_check_display_memory(struct drm_device *dev,
* SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM is not present vram size is
* limit on primary bounding box
*/
- if (pixel_mem > dev_priv->prim_bb_mem) {
+ if (pixel_mem > dev_priv->max_primary_mem) {
VMW_DEBUG_KMS("Combined output size too large.\n");
return -EINVAL;
}
@@ -1497,7 +1497,7 @@ static int vmw_kms_check_display_memory(struct drm_device *dev,
!(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {
bb_mem = (u64) bounding_box.x2 * bounding_box.y2 * 4;
- if (bb_mem > dev_priv->prim_bb_mem) {
+ if (bb_mem > dev_priv->max_primary_mem) {
VMW_DEBUG_KMS("Topology is beyond supported limits.\n");
return -EINVAL;
}
@@ -1897,7 +1897,7 @@ bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
{
return ((u64) pitch * (u64) height) < (u64)
((dev_priv->active_display_unit == vmw_du_screen_target) ?
- dev_priv->prim_bb_mem : dev_priv->vram_size);
+ dev_priv->max_primary_mem : dev_priv->vram_size);
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
index fefd7a71d764daef43a495e29c4bc29813f7a314..895088924ce3ab056298e2ce23cc27622270a223 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
@@ -37,14 +37,14 @@
#ifdef CONFIG_64BIT
#define VMW_PPN_SIZE 8
-#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH64_0
-#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH64_1
-#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH64_2
+#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT64_0
+#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT64_1
+#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT64_2
#else
#define VMW_PPN_SIZE 4
-#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH_0
-#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH_1
-#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH_2
+#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT_0
+#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT_1
+#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT_2
#endif
/*
@@ -70,20 +70,20 @@ struct vmw_mob {
* @page_table: Pointer to a struct vmw_mob holding the page table.
*/
static const struct vmw_otable pre_dx_tables[] = {
- {VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
+ {VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
+ {VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
+ {VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
+ {VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
+ {VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE}
};
static const struct vmw_otable dx_tables[] = {
- {VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
- {VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
+ {VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
+ {VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
+ {VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
+ {VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
+ {VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE},
{VMWGFX_NUM_DXCONTEXT * sizeof(SVGAOTableDXContextEntry), NULL, true},
};
@@ -155,7 +155,7 @@ static int vmw_setup_otable_base(struct vmw_private *dev_priv,
goto out_no_populate;
vmw_mob_pt_setup(mob, iter, otable->size >> PAGE_SHIFT);
- mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
+ mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
}
cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
@@ -636,7 +636,7 @@ int vmw_mob_bind(struct vmw_private *dev_priv,
vmw_mob_pt_setup(mob, data_iter, num_data_pages);
pt_set_up = true;
- mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
+ mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
}
vmw_fifo_resource_inc(dev_priv);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 9e236f9f8a8a132b6f4cee120102e27e1ac51f70..365ed93dd3e8a0aed61536ef0b2ce46a1b0d7372 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -33,7 +33,7 @@
#include <drm/drm_vblank.h>
#include "vmwgfx_kms.h"
-#include "device_include/svga3d_surfacedefs.h"
+#include "vmw_surface_cache.h"
#define vmw_crtc_to_stdu(x) \
container_of(x, struct vmw_screen_target_display_unit, base.crtc)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
index 47c03a2765151f820b3cfae1d5d6f4464cd9ee34..0eba47762bedf2e3137fc4afdfda7e52a23b053e 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
@@ -31,6 +31,7 @@
#include "vmwgfx_resource_priv.h"
#include "vmwgfx_so.h"
#include "vmwgfx_binding.h"
+#include "vmw_surface_cache.h"
#include "device_include/svga3d_surfacedefs.h"
#define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
@@ -78,7 +79,7 @@ struct vmw_surface_offset {
* @boxes: Array of SVGA3dBoxes indicating dirty regions. One per subresource.
*/
struct vmw_surface_dirty {
- struct svga3dsurface_cache cache;
+ struct vmw_surface_cache cache;
size_t size;
u32 num_subres;
SVGA3dBox boxes[];
@@ -307,8 +308,8 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
{
uint32_t i;
struct vmw_surface_dma *cmd = (struct vmw_surface_dma *)cmd_space;
- const struct svga3d_surface_desc *desc =
- svga3dsurface_get_desc(srf->metadata.format);
+ const struct SVGA3dSurfaceDesc *desc =
+ vmw_surface_get_desc(srf->metadata.format);
for (i = 0; i < srf->metadata.num_sizes; ++i) {
SVGA3dCmdHeader *header = &cmd->header;
@@ -323,8 +324,7 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
body->guest.ptr = *ptr;
body->guest.ptr.offset += cur_offset->bo_offset;
- body->guest.pitch = svga3dsurface_calculate_pitch(desc,
- cur_size);
+ body->guest.pitch = vmw_surface_calculate_pitch(desc, cur_size);
body->host.sid = srf->res.id;
body->host.face = cur_offset->face;
body->host.mipmap = cur_offset->mip;
@@ -342,7 +342,7 @@ static void vmw_surface_dma_encode(struct vmw_surface *srf,
suffix->suffixSize = sizeof(*suffix);
suffix->maximumOffset =
- svga3dsurface_get_image_buffer_size(desc, cur_size,
+ vmw_surface_get_image_buffer_size(desc, cur_size,
body->guest.pitch);
suffix->flags.discard = 0;
suffix->flags.unsynchronized = 0;
@@ -432,7 +432,7 @@ static int vmw_legacy_srf_create(struct vmw_resource *res)
goto out_no_id;
}
- if (unlikely(res->id >= SVGA3D_MAX_SURFACE_IDS)) {
+ if (unlikely(res->id >= SVGA3D_HB_MAX_SURFACE_IDS)) {
ret = -EBUSY;
goto out_no_fifo;
}
@@ -751,7 +751,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
struct vmw_surface_offset *cur_offset;
uint32_t num_sizes;
uint32_t size;
- const struct svga3d_surface_desc *desc;
+ const SVGA3dSurfaceDesc *desc;
if (unlikely(vmw_user_surface_size == 0))
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
@@ -772,8 +772,8 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
ttm_round_pot(num_sizes * sizeof(struct drm_vmw_size)) +
ttm_round_pot(num_sizes * sizeof(struct vmw_surface_offset));
- desc = svga3dsurface_get_desc(req->format);
- if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
+ desc = vmw_surface_get_desc(req->format);
+ if (unlikely(desc->blockDesc == SVGA3DBLOCKDESC_NONE)) {
VMW_DEBUG_USER("Invalid format %d for surface creation.\n",
req->format);
return -EINVAL;
@@ -833,13 +833,13 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data,
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
for (j = 0; j < metadata->mip_levels[i]; ++j) {
- uint32_t stride = svga3dsurface_calculate_pitch
- (desc, cur_size);
+ uint32_t stride = vmw_surface_calculate_pitch(
+ desc, cur_size);
cur_offset->face = i;
cur_offset->mip = j;
cur_offset->bo_offset = cur_bo_offset;
- cur_bo_offset += svga3dsurface_get_image_buffer_size
+ cur_bo_offset += vmw_surface_get_image_buffer_size
(desc, cur_size, stride);
++cur_offset;
++cur_size;
@@ -1711,10 +1711,10 @@ vmw_gb_surface_reference_internal(struct drm_device *dev,
* than partial z slices are dirtied.
*/
static void vmw_subres_dirty_add(struct vmw_surface_dirty *dirty,
- const struct svga3dsurface_loc *loc_start,
- const struct svga3dsurface_loc *loc_end)
+ const struct vmw_surface_loc *loc_start,
+ const struct vmw_surface_loc *loc_end)
{
- const struct svga3dsurface_cache *cache = &dirty->cache;
+ const struct vmw_surface_cache *cache = &dirty->cache;
SVGA3dBox *box = &dirty->boxes[loc_start->sub_resource];
u32 mip = loc_start->sub_resource % cache->num_mip_levels;
const struct drm_vmw_size *size = &cache->mip[mip].size;
@@ -1760,7 +1760,7 @@ static void vmw_subres_dirty_add(struct vmw_surface_dirty *dirty,
*/
static void vmw_subres_dirty_full(struct vmw_surface_dirty *dirty, u32 subres)
{
- const struct svga3dsurface_cache *cache = &dirty->cache;
+ const struct vmw_surface_cache *cache = &dirty->cache;
u32 mip = subres % cache->num_mip_levels;
const struct drm_vmw_size *size = &cache->mip[mip].size;
SVGA3dBox *box = &dirty->boxes[subres];
@@ -1783,15 +1783,15 @@ static void vmw_surface_tex_dirty_range_add(struct vmw_resource *res,
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
size_t backup_end = res->backup_offset + res->backup_size;
- struct svga3dsurface_loc loc1, loc2;
- const struct svga3dsurface_cache *cache;
+ struct vmw_surface_loc loc1, loc2;
+ const struct vmw_surface_cache *cache;
start = max_t(size_t, start, res->backup_offset) - res->backup_offset;
end = min(end, backup_end) - res->backup_offset;
cache = &dirty->cache;
- svga3dsurface_get_loc(cache, &loc1, start);
- svga3dsurface_get_loc(cache, &loc2, end - 1);
- svga3dsurface_inc_loc(cache, &loc2);
+ vmw_surface_get_loc(cache, &loc1, start);
+ vmw_surface_get_loc(cache, &loc2, end - 1);
+ vmw_surface_inc_loc(cache, &loc2);
if (loc1.sheet != loc2.sheet) {
u32 sub_res;
@@ -1811,12 +1811,12 @@ static void vmw_surface_tex_dirty_range_add(struct vmw_resource *res,
vmw_subres_dirty_add(dirty, &loc1, &loc2);
} else {
/* Dirty range covers multiple sub-resources */
- struct svga3dsurface_loc loc_min, loc_max;
+ struct vmw_surface_loc loc_min, loc_max;
u32 sub_res;
- svga3dsurface_max_loc(cache, loc1.sub_resource, &loc_max);
+ vmw_surface_max_loc(cache, loc1.sub_resource, &loc_max);
vmw_subres_dirty_add(dirty, &loc1, &loc_max);
- svga3dsurface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
+ vmw_surface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
vmw_subres_dirty_add(dirty, &loc_min, &loc2);
for (sub_res = loc1.sub_resource + 1;
sub_res < loc2.sub_resource - 1; ++sub_res)
@@ -1833,7 +1833,7 @@ static void vmw_surface_buf_dirty_range_add(struct vmw_resource *res,
{
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
- const struct svga3dsurface_cache *cache = &dirty->cache;
+ const struct vmw_surface_cache *cache = &dirty->cache;
size_t backup_end = res->backup_offset + cache->mip_chain_bytes;
SVGA3dBox *box = &dirty->boxes[0];
u32 box_c2;
@@ -1876,7 +1876,7 @@ static int vmw_surface_dirty_sync(struct vmw_resource *res)
struct vmw_surface_dirty *dirty =
(struct vmw_surface_dirty *) res->dirty;
size_t alloc_size;
- const struct svga3dsurface_cache *cache = &dirty->cache;
+ const struct vmw_surface_cache *cache = &dirty->cache;
struct {
SVGA3dCmdHeader header;
SVGA3dCmdDXUpdateSubResource body;
@@ -1989,7 +1989,7 @@ static int vmw_surface_dirty_alloc(struct vmw_resource *res)
}
num_samples = max_t(u32, 1, metadata->multisample_count);
- ret = svga3dsurface_setup_cache(&metadata->base_size, metadata->format,
+ ret = vmw_surface_setup_cache(&metadata->base_size, metadata->format,
num_mip, num_layers, num_samples,
&dirty->cache);
if (ret)
@@ -2080,7 +2080,7 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
*srf_out = NULL;
if (req->scanout) {
- if (!svga3dsurface_is_screen_target_format(req->format)) {
+ if (!vmw_surface_is_screen_target_format(req->format)) {
VMW_DEBUG_USER("Invalid Screen Target surface format.");
return -EINVAL;
}
@@ -2095,10 +2095,10 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
return -EINVAL;
}
} else {
- const struct svga3d_surface_desc *desc =
- svga3dsurface_get_desc(req->format);
+ const SVGA3dSurfaceDesc *desc =
+ vmw_surface_get_desc(req->format);
- if (desc->block_desc == SVGA3DBLOCKDESC_NONE) {
+ if (desc->blockDesc == SVGA3DBLOCKDESC_NONE) {
VMW_DEBUG_USER("Invalid surface format.\n");
return -EINVAL;
}
@@ -2147,11 +2147,12 @@ int vmw_gb_surface_define(struct vmw_private *dev_priv,
sample_count = metadata->multisample_count;
srf->res.backup_size =
- svga3dsurface_get_serialized_size_extended(metadata->format,
- metadata->base_size,
- metadata->mip_levels[0],
- num_layers,
- sample_count);
+ vmw_surface_get_serialized_size_extended(
+ metadata->format,
+ metadata->base_size,
+ metadata->mip_levels[0],
+ num_layers,
+ sample_count);
if (metadata->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
srf->res.backup_size += sizeof(SVGA3dDXSOState);